A substrate fabrication system is provided which includes a buffer station located inline between a front docking port and a loadlock chamber, the buffer station being operatively joined with a front handling chamber. Preferred embodiments employ a buffer station having a rack with reduced pitch, or relative spacing between shelves. Additional embodiments provide variable pitch end effectors as part of the disclosed fabrication system.
1. A semiconductor processing tool comprising:
a first substrate handling chamber; a front docking port located on the outside surface of the first substrate chamber; a robot arm located in the front wafer handling chamber; a loadlock chamber joined to the first substrate handling chamber; and a buffer station located between the loadlock chamber and the front docking ports, the buffer station being configured to provide a less contaminated inert internal environment as compared with the internal environment of a cassette docked to the docking port, the buffer station having a rack configured to have multiple shelves for holding substrates. 2. The semiconductor processing tool according to 3. The semiconductor processing tool according to 4. The semiconductor processing tool according to 5. The semiconductor processing tool according to 6. The semiconductor processing tool according to 7. The semiconductor processing tool according to 8. The semiconductor processing tool according to 9. The semiconductor processing tool according to 10. The semiconductor processing tool according to 11. The semiconductor processing tool according to 12. The semiconductor processing tool according to 13. The semiconductor processing tool according to 14. A semiconductor processing tool comprising:
a substrate handling chamber; a front docking port located on an outside surface of the substrate handling chamber, the port being capable of mating with a cassette; a cassette rack internal to the docked cassette; a purgeable buffer station joined with the substrate handling chamber, the buffer station being located in position downstream of the front docking port; and a buffer station rack within the buffer station being configured to have multiple slots for holding substrates. 15. The semiconductor processing tool according to 16. The semiconductor processing tool according to 17. The semiconductor processing tool according to 18. The semiconductor processing tool according to 19. The semiconductor processing tool according to 20. The semiconductor processing tool according to 21. The semiconductor processing tool according to 22. The semiconductor processing tool according to 23. The semiconductor processing tool according to
[0001] This application is a divisional of U.S. application Ser. No. 10/260,821, filed on Sep. 27, 2002. [0002] The present invention relates generally to semiconductor fabrication, and more particularly to improved wafer handling systems. [0003] Semiconductor wafers or other such substrates typically arrive at the input of a process tool as a group carried in a wafer carrier and from this input must be transported among the internal stations of a process tool. In furtherance of this task, wafer handling systems facilitate the transfer of wafers from one station to another. During this process, it is very important that the wafer be kept isolated from contamination. The presence of contaminant particles on the surface of a wafer can lead to the formation of defects during the fabrication process. Therefore, the wafers must be moved between isolated interior chambers of a process tool in such away as to minimize contamination of both the wafers themselves and the possibility of the cross contamination of chambers. [0004] In furtherance of minimizing wafer contamination, it is desirable to minimize the amount of time a wafer is exposed to contaminants. One way to minimize contaminants is to use standardized front opening unified pods (FOUPs). [0005] Another approach to minimizing wafer exposure to the ambient environment (e.g., clean room) is to use a large capacity loadlock chamber (e.g., 25 wafers) capable of receiving an entire cassette or FOUP of wafers. However, large capacity loadlock chambers pose a number of problems including requiring complex elevator mechanisms, which require an even larger volume. The elevator mechanisms require extra chamber “headroom” in order to have space to raise and lower the load of wafers, allowing access by single wafer robots. Due to the large internal volume of high capacity loadlock chambers, longer purge cycles are necessary to remove potentially wafer damaging agents, such as oxygen and moisture. During these purge cycles, wafer processing is delayed while waiting on the completion of the purging. In systems where two loadlock chambers are employed the footprint of the fabrication tool can also increase substantially. In addition, the use of an elevator mechanism reduces the uptime and system availability, and further increases the risk of particle generation caused by the moving components of the elevator. [0006] Wafer handling systems typically employ robot arms in order to effectively transfer wafers between stations. On the end of each of these arms, an end effector is configured to gain access to a wafer at a first station, lift the wafer, transport the wafer, gain access to the second station, and then deposit the wafer at the second station. [0007] The cost of processing semiconductor wafers, always a prime consideration, is often evaluated by the throughput per unit of cost. Another measure of cost is the throughput per area of floor space, wherein it is desirable to reduce the footprint of the apparatus employed. Related to both is the importance of reducing the capital cost of the equipment. In an industry in which the speed of processing is directly related to output, additional handling steps slow down the fabrication line. Therefore, advancements that can improve the competitive edge by either measure are highly desirable. [0008] In accordance with one aspect of the present invention, a semiconductor processing tool is provided comprising a first substrate handling chamber, a front docking port located on the outside surface of the first substrate chamber, and a robot arm located in the front wafer handling chamber. In addition, a loadlock chamber is joined to the first substrate handling chamber and a buffer station is located between the loadlock chamber and the front docking ports. The buffer station is configured to provide a less contaminated inert internal environment as compared with the internal environment of a cassette docked to the docking port. The buffer station also has a rack configured to have multiple shelves for holding substrates. [0009] In accordance with one aspect of the present invention, a method of fabricating an integrated circuit is also provided comprising first docking a substrate cassette with a front docking port of a process tool. A substrate is then transferred to a buffer station located between the docking port and a loadlock chamber and the buffer station is then purged. The substrate is then moved from the buffer station to the loadlock chamber. [0010] Preferred embodiments of the present invention employ a buffer station having a rack with reduced pitch, or relative spacing between shelves, as compared to standard cassettes or FOUPs for the same size of substrate. Thus, the preferred buffer stations have a low volume that can be quickly and efficiently purged to provide a clean, nonoxidizing environment. [0011] The preferred embodiments offer many advantages. Embodiments employing buffer chambers, which are small and easily purged, serve as quickly accessible and less contaminated chambers to temporarily store wafers during processing. Reduced pitch buffer station racks also enable access to all shelves by a standard robot arm, without the need for a internal elevator mechanism in the buffer stations. Consequently, the absence of the extra movement inherent with an internal elevator decreases the generation of contaminants inside the process tool. [0012] Certain preferred embodiments employ a variable pitch end effector in order to adjust the relative spacing of the end effector wafer supports. This allows the end effector to simultaneously transfer a plurality of wafers between racks, even though the racks have a different relative spacings between support slots shelves. [0013] For purposes of summarizing the invention and the advantages achieved over the prior art, certain objects and advantages of the invention have been described herein above. Of course, it is to be understood that not necessarily all such objects or advantages may be achieved in accordance with any particular embodiment of the invention. Thus, for example, those skilled in the art will recognize that the invention may be embodied or carried out in a manner that achieves or optimizes one advantage or group of advantages as taught herein without necessarily achieving other objects or advantages as may be taught or suggested herein. [0014] All of these embodiments are intended to be within the scope of the invention herein disclosed. These and other embodiments of the present invention will become readily apparent to those skilled in the art from the following detailed description of the preferred embodiments having reference to the attached figures, the invention not being limited to any particular preferred embodiment(s) disclosed. [0015] [0016] [0017] [0018] [0019] [0020] [0021] [0022] [0023] [0024] [0025] [0026] [0027] [0028] [0029] Maximizing throughput while limiting both wafer handling and the exposure of a wafer to contamination are paramount goals, which preferred embodiments of the present invention advance. Long wafer handling times greatly limit a process tool's throughput. This limitation on throughput is not the only negative effect of longer wafer handling times, because the majority of the wafers must be left exposed to the ambient environment of the clean room, as compared to the more controlled environment within the process tool, while a batch is transferred. This long exposure can be unacceptable when a wafer must be transferred quickly to protect delicate surface conditions or to prevent growth of an unwanted native oxide layer. Even the intermediate purity levels defined between an enclosed front end interface chamber and a docked front opening unified pod (FOUP) can cause unacceptable particle and oxide formation during such extended exposure. [0030] One possible approach to minimizing wafer exposure to the clean room atmosphere is to use low capacity (e.g. 1 to 7 wafers) loadlock chambers. A small capacity loadlock chambers has less internal volume and, thus, can be purged much more quickly than a large capacity loadlock chamber. However, the reduced capacity of the loadlock chamber creates additional disadvantages. For instance, if up to 50 wafers (i.e. two full cassettes or FOUPs) arrive at the system at once, then many of the wafers will remain in the clean room or front end interface environment for a significant amount of time while the system processes wafers in small number lots. [0031] Accordingly, the preferred embodiments employ a low capacity loadlock chamber in conjunction with higher capacity, but low volume purgeable buffer station in order to, among other goals, alleviate the throughput and contamination disadvantages of using low capacity loadlock chambers. [0032] Preferred buffer stations also employ racks having reduced pitch or spacing between the shelves or slots forming the rack, relative to the standard pitch in a cassette or FOUP designed for the same size substrates. A feature of these reduced pitch racks is that they allow the volume of a buffer station to be reduced in order to allow the station to be more quickly purged. The height of the uppermost slot is thus low enough to be reached within the vertical range of a standard robot. Such a standard robot is commercially available, for example, from Asyst Technologies, Inc. of Fremont, Calif. Such a robot has a vertical range of less than 30.5 cm. Use of such a standard robot and a reduced pitch buffer station rack obviates the use of elevator mechanisms to vertically shift the racks in order to reach all of the rack positions within the robot's vertical or “z” range, and also obviates modifying the robot to have greater vertical reach. [0033] Although in certain situations using a single wafer end effector is sufficient to transfer wafers among the storage racks of the preferred embodiment (FOUP, buffer station and loadlock racks), in other situations this practice is too slow. With the use of single wafer end effectors the transfer of each wafer requires a complete cycle. A cycle is defined as picking up a wafer from a first station and depositing the wafer in a second station, and then returning to the first station. Therefore, an entire cycle must be completed in order to transfer one wafer, thus requiring 25 cycles to transfer 25 wafers. In modern high input wafer fabrication systems, the total number of cycles required to transfer a large number of wafers can be a significant throughput limiting factor, especially where process times are short and wafer handling is the limiting factor. In an industry in which the speed of processing is directly related to output, the additive effect of these additional handling steps can significantly slow down the fabrication line. For example, if each cycle takes 12 seconds, it could take 300 seconds before the 25th wafer is transferred. Moreover, the wafer remains exposed to the clean room or the FOUP environment in the interim, subject to oxidation. [0034] Accordingly, a preferred embodiment also employs a multi-wafer transport system that significantly decreases the amount of time required to transport a group of wafers (e.g., a five wafer transfer system would cut the total transfer time of 25 wafer by 80%). Multiple wafer end effectors are described below with respect to FIGS. 5-7B. [0035] Referring now to [0036] The robot arm 24 is further configured to allow access to a buffer station 30. The buffer station 30, which is preferably separated from the AFE chamber 22 by buffer station doors 13, preferably has both pump down and purging capabilities facilitated by a purge valve 34 and gas inlet 36. In one preferred embodiment, the buffer station 30 has a reduced pitch buffer station rack 38 ( [0037] It should also be understood that in other arrangements of the process tool, the position which the buffer station occupies is advantageously used for a completely different function, such as replacing the buffer station with a pre-processing station or a post-processing station, with minimal increase in the size of the tool footprint. For example, the buffer station can be replaced by a pre-clean station, such as an etch station, or a postprocessing station where processes such as annealing or the deposition of other layers, such as a sealing oxide layer, are conducted. In yet other arrangements, the buffer station is capable of being replaced by a metrology tool without the need to substantially change the system configuration. [0038] A loadlock chamber 40, preferably a low-capacity loadlock chamber, is also adjoined to the AFE chamber 22, the loadlock chamber 40 being accessed by the robot arm 24 via a gate valve or door 42. The loadlock chamber 40 is located to serve as a selectively closeable passageway between the AFE chamber 22 and a wafer handling chamber (WHC) 44, with a gate valve or door 42 on each end of the loadlock chamber 40. In alternate embodiments the load lock 40 can lead directly to a process chamber. Inside the loadlock chamber 40 is a loadlock rack 46 ( [0039] [0040] [0041] [0042] Referring now to [0043] With reference still to FIGS. 3A-3C, the operation of the embodiments shown in [0044] Once the desired number of wafers 20 have been transferred from the cassette rack 16 to the buffer station rack 38, the robot arm 24 unloads wafers 20 from the buffer station rack 38 and places the wafers 20 onto the loadlock rack 46, as needed for processing. Preferably, wafers 20 in need of processing are unloaded in the loadlock rack 46 by the robot arm 24, while those wafers which have already been processed are preferably shuttled back to the buffer station rack 38 on the robot arm's return trip. In one arrangement, processed wafers are stored in a one buffer station 30, while unprocessed wafers are stored in a separate buffer station 30 on the other side of the AFE chamber 22. The robot arm 24 preferably is programmed to continue to cycle between the buffer station 30 and the loadlock 40 until all wafers 20 are processed, before transferring wafers 20 back to the cassette rack 16. [0045] In alternate embodiments the robot arm and end effector are programmed to transfer a wafer from the loadlock rack and directly return the wafer to a cassette rack. In another embodiment, the buffer station includes an oxygen source (not shown) connected to the gas inlet 36 ( [0046] Referring now to [0047] Each buffer station 30 contains a buffer station rack 38, preferably with a low pitch relative to standard cassettes for the same size wafers, as described with respect to the previous embodiment. Preferably, each buffer station 30 also employs a purge valve 34 and gas inlet 36 for purging and pumping down the interior of the buffer station 30. Similarly, the buffer stations 30 preferably also possess doors 13 which allow the chamber to be selectively sealed from the AFE chamber 22. [0048] Inside each of the loadlock chambers 40 is a loadlock rack 46, preferably a low capacity loadlock rack. Behind the loadlock chambers is a wafer handling chamber (WHC) 44, in which a WHC robot 56 is positioned to have effective access to both the loadlock chambers 40 and the interior of a plurality of individual process chambers 58. The loadlock chambers 40 and the process chambers 58 are also preferably selectively sealable from the WHC chamber 44 through the use of gate valves 60. In preferred embodiments, a clean room wall 62 defines a “gray room” environment to which wafers are not exposed while the cassettes 10 are located on the clean room side of the wall 62, which is cleaner. In an alternate embodiment, the clean room wall 62 may be placed closer to the process chambers 58 or completely absent from the fabrication tool setup. [0049] Referring now to [0050] In operation, the variable pitch multi-wafer end effector 48 preferably functions in a manner similar to the embodiment shown in [0051] Referring again to [0052] Although in preferred embodiments the cassette rack, buffer station rack and loadlock rack all support individual wafers by using slots, it should be understood that alternate embodiments can employ shelves or other suitable wafer support structures which facilitate the desired relative spacing between wafers. Also, though end effectors 48 are illustrated as underlying wafers (e.g., paddle), the skilled artisan will appreciate that other types of end effectors (e.g., edge grip, Bernoulli wand, etc.) can be employed with a variable pitch mechanism. [0053] With reference to [0054] Referring now to [0055] Note that while illustrated and discussed in conjunction with the buffer station having a reduced pitch relative to a FOUP, the skilled artisan will readily appreciate that the variable pitch end effectors and methods described herein are applicable to transfer among a variety of racks having different pitches from one another. For example, the adjustable pitch end effector could be used to transfer wafers between a FOUP and a shipping container, the container having a different pitch relative to the FOUP. [0056] A preferred method of fabricating integrated circuits is shown in [0057] A feature of certain preferred embodiments of the present invention is that the facilitation of a quick transfer of a load of wafers arriving at a docking port from the atmosphere in the cassette to an inert environment within the purgeable buffer stations. [0058] Another feature of certain preferred embodiments of the present invention is the use of reduced pitch buffer racks which enable buffer stations to have smaller volumes, thus enabling faster purging of the interior of the buffer station subsequent to a load of wafers arriving. This feature increases throughput and minimizes the level of contamination to which individual wafers are subjected. [0059] Yet another advantage of certain embodiments of the present invention is the facilitation of the simultaneous transfer of multiple wafers between racks having unequal pitch or spacing relative to one another. These pitch differences enable the use of standard pitch cassettes with both low volume buffer stations and loadlock chambers, which are more easily purged. In addition, preferred embodiments also minimize the exposure of a wafer to contaminating particles. [0060] An additional feature of certain embodiments of the present invention is the use of reduced pitch buffer station racks in order to facilitate a robot arm accessing the entire reduced pitch buffer station rack through the use of the robot arm's z-motion alone without necessitating an internal elevator mechanism and the added complexity and potential contamination caused by elevator mechanisms. [0061] Although this invention has been disclosed in the context of certain preferred embodiments and examples, it will be understood by those skilled in the art that the present invention extends beyond the specifically disclosed embodiments to other alternative embodiments and/or uses of the invention and obvious modifications thereof. Thus, it is intended that the scope of the present invention herein disclosed should not be limited by the particular disclosed embodiments described above, but should be determined only by a fair reading of the claims that follow. REFERENCE TO RELATED APPLICATION
FIELD OF THE INVENTION
BACKGROUND OF THE INVENTION
SUMMARY OF THE INVENTION
BRIEF DESCRIPTION OF THE DRAWINGS
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS