Analog circuits having improved insulated gate transistors, and methods therefor

A circuit can include at least one pair of deeply depleted channel (DDC) transistors having sources commonly coupled to a same current path; and a bias circuit configured to provide bias currents to the drains of the DDC transistors; wherein each DDC transistor includes a source and drain doped to a first conductivity type, a substantially undoped channel region, and a highly doped screening region of the first conductivity type formed below the channel region.

1. A circuit, comprising:

at least one pair of deeply depleted channel (DDC) transistors having sources commonly coupled to a same current path; and

a bias circuit configured to provide bias currents to the drains of the DDC transistors; wherein

each DDC transistor includes a source and drain doped to a first conductivity type, a substantially undoped channel region extending laterally between the source and drain and contacting the source and drain, and a highly doped screening region of a second conductivity type, the highly doped screening region formed below the channel region and extending laterally between the source and drain.

2. The circuit of claim 1, wherein:

the circuit comprises a current mirror circuit that provides an output current in response to a reference current;

the pair of DDC transistors have gates commonly coupled to one another and to a drain of a first of the DDC transistors, and bodies commonly coupled to their gates; and

the bias circuit is configured to provide the reference current to the drain of the first DDC transistor.

3. The circuit of claim 1, further including:

the circuit comprises an operational amplifier circuit configured to amplify an input voltage received at input nodes;

the pair of DDC transistors includes

a first input DDC transistor with a gate coupled to a first input node, and

a second input DDC transistor with a gate coupled to a second input node; and

an output stage comprising a driver transistor coupled to an output node, the driver transistor being controlled in response to a current flowing through the first input DDC transistor.

4. The circuit of claim 3, wherein:

the bodies of the first and second input DDC transistors have bodies commonly coupled to a source of one of the input DDC transistors.

5. The circuit of claim 3, wherein:

the body of the first input DDC transistor is coupled to its gate; and

the body of the second input DDC transistor is coupled to its gate.

6. The circuit of claim 3, wherein:

the bias circuit comprises a current mirror circuit formed of at least one pair of mirror DDC transistors of a conductivity type opposite to that of the input DDC transistors, the mirror DDC transistors having gates commonly coupled to one another and to a drain of a first of the mirror DDC transistors, and bodies commonly coupled to their gates.

7. The circuit of claim 1, wherein:

the circuit is configured to operate with a power supply voltage of less-than-or-equal to 0.5 volts.

8. The circuit of claim 1, wherein:

the highly doped screening region has a dopant concentration of no less than 5×10¹⁸.

9. The circuit of claim 1, wherein:

the highly doped screening region contacts the source and drain.

10. A circuit, comprising:

a plurality of inverting stages coupled to one another in series, an output of a last stage being coupled to an input of a first stage; and

each stage comprising at least two deeply depleted channel (DDC) transistors having gates coupled to a stage input, and configured to drive a stage output between two different voltages; wherein

each DDC transistor includes a source and drain doped to a first conductivity type, a substantially undoped channel region extending laterally between the source and drain and contacting the source and drain, and a highly doped screening region of a second conductivity type, the highly doped screening region formed below the channel region and extending laterally between the source and drain.

11. The circuit of claim 10, wherein:

each stage comprises a first DDC transistor of a first conductivity type and a second DDC transistor of a second conductivity type having drains commonly coupled to the stage output.

12. The circuit of claim 10, wherein:

each stage includes the bodies of the DDC transistors coupled to their gates.

13. The circuit of claim 10, further including:

a stage capacitance coupled between each stage, each stage capacitance comprising a load DDC transistor.

14. The circuit of claim 13, wherein:

each load DDC transistor has gate coupled to a first capacitance terminal and a source and drain commonly coupled to a second capacitance terminal.

15. The circuit of claim 13, wherein:

each stage capacitance comprises a varactor, with the body of each load DDC transistor coupled to a first voltage source and the source and drain of each load transistor coupled to a second voltage source; wherein

the capacitance of the varactor varies in response to the first and second voltage sources.

16. The circuit of claim 10, further including:

the circuit is configured to operate with a power supply voltage of less-than-or-equal to 0.5 volts.

17. The circuit of claim 10, wherein:

the highly doped screening region contacts the source and drain.

18. A circuit, comprising:

at least one varactor element comprising at least a first deeply depleted channel (DDC) transistor having a gate coupled to a first terminal, source and drain coupled to a second terminal, and a body coupled to a third terminal;

a first bias circuit coupled to apply a first bias voltage to the third terminal; and

a second bias circuit coupled to apply a second bias voltage to the second terminal; wherein

each DDC transistor includes a source and drain doped to a first conductivity type, a substantially undoped channel region extending laterally between the source and drain and contacting the source and drain, and a highly doped screening region of a second conductivity type formed below the channel region and extending laterally between the source and drain, and wherein a capacitance between the first and second terminals varies in response to the first and second bias voltages.

19. The circuit of claim 18, wherein:

each varactor element further includes a second DDC transistor having a gate coupled to a fourth terminal, source and drain coupled to the second terminal, and a body coupled to the third terminal; wherein

a capacitance between the first and fourth terminals varies in response to the first and second bias voltages.

20. The circuit of claim 18, further including:

a plurality of inverting stages coupled to one another in series, an output of a last stage being coupled to an input of a first stage; and

the at least one varactor element includes a plurality of varactor elements, each having a first terminal coupled to an output of each stage.

21. The circuit of claim 18, further including:

the varactor element further includes a second DDC transistor having a gate coupled to a fourth terminal, source and drain coupled to the second terminal, and a body coupled to the third terminal;

a first inductor coupled between the first terminal and a power supply terminal; and

a second inductor coupled between the fourth terminal and the power supply terminal.

22. The circuit of claim 18, wherein:

the at least one varactor element has a capacitance tuning range more than 15% greater than the tuning range of a varactor element formed with a same sized transistor that does not include a substantially undoped channel region or a highly doped screening region.

23. The circuit of claim 18, wherein:

the highly doped screening region contacts the source and drain.

This application claims the benefit of U.S. Provisional Applications Ser. No. 61/545,006, filed on Oct. 7, 2011 and Ser. No. 61/545,014, also filed on Oct. 7, 2011, the contents of which are incorporated by reference herein, in their entirety.

The present invention relates generally to analog circuits, and more particularly to analog circuits formed with insulated gate field effect transistors having a body bias connections.

Various embodiments of the present invention will now be described in detail with reference to a number of drawings. The embodiments show analog circuits having transistors with structures that provide for greater gain than conventional approaches. In particular embodiments, transistors can have a highly doped “screening” region formed below a channel that can be biased via a body terminal. Embodiments as described herein can be applicable to integrated circuits that include analog circuits, or mixes of analog and digital circuits.

FIG. 1 shows a block schematic diagram of a circuit 100 according to one embodiment. A circuit 100 can include a pair of deeply depleted channel (DDC) transistors 102-0/1, a bias circuit 104, and a current path 108. DDC transistors 102-0/1 can each have a gate (G), source (S), drain (D) and body (B) terminal. Drains (D) can be connected to bias circuit 104, sources (S) can be commonly connected to current path 108. DDC transistors are insulated gate field effect transistors (referred to herein as “MOS” transistors) having a highly doped screening region (described below) that can be biased to provide for greater gain than conventional MOS transistors.

A bias circuit 104 can provide current to the drains (D) of DDC transistors 102-0/1, and can be connected to a first power supply terminal 106-0. A current path 108 can provide a current path between sources (S) of DDC transistors 102-0/1 and a second power supply terminal 106-1.

DDC transistors 102-0/1 can provide higher gain than conventional transistors, if the input signal is applied to both the gate and the screening region. While FIG. 1 shows n-channel transistors, such transistors can be p-channel transistors in other embodiments.

FIG. 2A shows an embodiment of a deeply depleted channel (DDC) transistor 200 having an enhanced body coefficient, along with the ability to set threshold voltage Vt with enhanced precision, according to certain described embodiments. The DDC transistor 200 includes a gate electrode 210, source 212, drain 214, and a gate dielectric 216 positioned over a substantially undoped channel 218. Lightly doped source and drain extensions (SDE) 220, positioned respectively adjacent to source 212 and drain 214, extend toward each other, setting the transistor channel length (L_G). In the embodiment shown, insulating spacers 221 can be formed on sides of gate electrode 210.

In FIG. 2A, the DDC transistor 200 is shown as an N-channel transistor having a source 212 and drain 214 made of N-type dopant material, formed upon a substrate such as a P-type doped silicon substrate providing a P-well 222 formed on a substrate 224. In addition, the N-channel DDC transistor in FIG. 2 includes a highly doped screening region 226 made of P-type dopant material, and a threshold voltage set region 228 made of P-type dopant material. Screening region 226 can be biased via a body tap 230. It will be understood that, with appropriate changes to dopant materials, a P-channel DDC transistor can be formed.

FIG. 2B is a flow diagram 232 illustrating a general method for forming a DDC transistor having an enhanced body coefficient and reduced σ Vt, in accordance with the various embodiments described herein. The process illustrated in FIG. 1B is intended to be general and broad in its description, and more detailed embodiments and examples are set forth below. Each block in the flow diagram is illustrated and described in further detail below, in conjunction with the various alternatives associated with each block illustrated in FIG. 2B.

In step 234, the process begins at well formation, which can include one or more different process steps in accordance with different embodiments. The well formation step 234 includes the steps for forming the screening region 226, the threshold voltage set region 228 (if present), and the substantially undoped channel 218. As indicated by 236, the well formation 234 can be before or after STI (shallow trench isolation) formation 238.

The well formation 234 can include forming the screening region 226 by implanting dopants into the P-well 222, followed by an epitaxial (EPI) pre-clean process that is followed by a blanket or selective EPI deposition. Various alternatives for performing these steps are illustrated in FIG. 2B. In accordance with one embodiment, well formation 234 can include a beam line implant of Ge/B (N), As (P), followed by an epitaxial (EPI) pre-clean process, and followed by a non-selective blanket EPI deposition, as shown in 234A.

Alternatively, the well formation 234 can include using a plasma implant of B (N), As (P), followed by an EPI pre-clean, then a non-selective (blanket) EPI deposition, as shown in 234B. The well formation 234 can alternatively include a solid-source diffusion of B(N), As(P), followed by an EPI pre-clean, and followed by a non-selective (blanket) EPI deposition, as shown in 234C. As yet another alternative, well formation 234 can also include well implants, followed by in-situ doped selective EPI of B (N), P (P) as shown in 234D. As will be described further below, the well formation can be configured with different types of devices in mind, including DDC transistors, legacy transistors, high V_Ttransistors, low V_Ttransistors, improved σV_Ttransistors, and standard or legacy σV_Ttransistors. Embodiments described herein allow for any one of a number of devices configured on a common substrate with different well structures and according to different parameters.

In step 234, Boron (B), Indium (I), or other P-type materials can be used for P-type implants, and arsenic (As), antimony (Sb) or phosphorous (P) and other N-type materials can be used for N-type implants. In certain embodiments, the screening region 226 can have a dopant concentration between about 5×10¹⁸to 1×10²⁰dopant atoms/cm³, with the selected dopant concentration dependent on the desired threshold voltage as well as other desired transistor characteristics. A germanium (Ge), carbon (C), or other dopant migration resistant layer can be incorporated above the screening region to reduce upward migration of dopants. The dopant migration resistant layer can be formed by way of ion implantation, in-situ doped epitaxial growth or other process. In certain embodiments, a dopant migration resistant layer can also be incorporated to reduce downward migration of dopants.

In certain embodiments of the DDC transistor, a threshold voltage set region 228 is positioned above the screening region 226. The threshold voltage set region 228 can be either adjacent to, incorporated within or vertically offset from the screening region. In certain embodiments, the threshold voltage set region 228 is formed by delta doping, controlled in-situ deposition, or atomic layer deposition. In alternative embodiments, the threshold voltage set region 226 can be formed by way of controlled outdiffusion of dopant material from the screening region 226 into an undoped epitaxial layer, or by way of a separate implantation into the substrate following formation of the screening region 226, before the undoped epitaxial layer is formed. Setting of the threshold voltage for the transistor is implemented by suitably selecting dopant concentration and thickness of the threshold voltage set region 228, as well as maintaining a separation of the threshold voltage set region 228 from the gate dielectric 216, leaving a substantially undoped channel layer directly adjacent to the gate dielectric 216. In certain embodiments, the threshold voltage set region 228 can have a dopant concentration between about 1×10¹⁸dopant atoms/cm³and about 1×10¹⁹dopant atoms per cm³. In alternative embodiments, the threshold voltage set region 228 can have a dopant concentration that is approximately less than half of the concentration of dopants in the screening region 226.

In certain embodiments, an over-layer of the channel is formed above the screening region 226 and threshold voltage set region 228 by way of a blanket or selective EPI deposition (as shown in the alternatives shown in 234A-D), to result in a substantially undoped channel region 218 of a thickness tailored to the technical specifications of the device. As a general matter, the thickness of the substantially undoped channel region 218 ranges from approximately 5-25 nm, with the selected thickness based upon the desired threshold voltage for the transistor. Preferably, a blanket EPI deposition step is performed after forming the screening region 226, and the threshold voltage setting region 228 is formed by controlled outdiffusion of dopants from the screening region 226 into a portion of the blanket EPI layer, as described below. Dopant migration resistant layers of C, Ge, or the like can be utilized as needed to prevent dopant migration from the threshold voltage set region 228 into the substantially undoped channel region 218, or alternatively from the screening region 226 into the threshold voltage set region 228.

In addition to using dopant migration resistant layers, other techniques can be used to reduce upward migration of dopants from the screening region 226 and the threshold voltage set region 228, including but not limited to low temperature processing, selection or substitution of low migration dopants such as antimony or indium, low temperature or flash annealing to reduce interstitial dopant migration, or any other technique to reduce movement of dopant atoms can be used.

As described above, the substantially undoped channel region 218 is positioned above the threshold voltage set region 228. Preferably, the substantially undoped channel region 218 has a dopant concentration less than 5×10¹⁷dopant atoms per cm³adjacent or near the gate dielectric 216. In some embodiments, the substantially undoped channel region 218 can have a dopant concentration that is specified to be approximately less than one tenth of the dopant concentration in the screening region 226. In still other embodiments, depending on the transistor characteristics desired, the substantially undoped channel region 218 may contain dopants so that the dopant concentration is elevated to above 5×10¹⁷dopant atoms per cm³adjacent or near the gate dielectric 216 or by using a very light dose of halo implants. Preferably, the substantially undoped channel region 218 remains substantially undoped by avoiding the use of high dosage halo or other channel implants.

Referring still to FIG. 2B, STI formation 238, which, again, can occur before or after well formation 234, can include a low temperature trench sacrificial oxide (TSOX) liner, which is formed at a temperature lower than 900° C. as shown by 238A. Embodiments that form the STI structures after the blanket EPI deposition step, using a process that remains within a low thermal budget, can reduce dopant migration from the previously formed screening region 226 and threshold voltage setting region 228.

As shown in step 240 (FIG. 2B), a gate stack can be formed or otherwise constructed above the substantially undoped channel region 218 in a number of different ways, from different materials, and of different work functions. One option is a polysilicon(Poly)/SiON gate stack 240A. Another option is a gate-first process 240B that includes SiON/Metal/Poly and/or SiON/Poly, followed by High-K/Metal Gate. Another option, a gate-last process 240C includes a high-K/metal gate stack wherein the gate stack can either be formed with “Hi-K first-Metal gate last” flow or and “Hi-K last-Metal gate last” flow. Yet another option, 240D is a metal gate that includes a tunable range of work functions depending on the device construction. Preferably, the metal gate materials for n-channel MOS (NMOS) and p-channel MOS (PMOS) are selected to near mid-gap, to take full advantage of the DDC transistor. However, traditional metal gate work function band-gap settings may also be used. In one scheme, metal gate materials can be switched between NMOS and PMOS pairs as a way to attain the desired work functions for given devices.

A gate stack may be formed or otherwise constructed above the substantially undoped channel region 218 in a number of different ways, from different materials including polysilicon and metals to form what is known as “high-k metal gate”. The metal gate process flow may be “gate 1^st” or “gate last”. Preferably, the metal gate materials for NMOS and PMOS are selected to near mid-gap, to take full advantage of the DDC transistor. However, traditional metal gate work function band-gap settings may also be used. In one scheme, metal gate materials can be switched between NMOS and PMOS pairs as a way to attain the desired work functions for given devices. Following formation of the gate stack, source/drain portions may be formed. Typically, the extension portions are implanted, followed by additional spacer formation and then implant or, alternatively, selective epitaxial deposition of deep source/drain regions.

In step 242, Source/Drain tips can be implanted. The dimensions of the tips can be varied as required, and will depend in part on whether gate spacers (SPGR) are used. In one embodiment, Source/Drain tips are not formed (step 242A), and there may be no tip implant.

In step 244, the source 212 and drain 214 can be formed preferably using conventional processes and materials such as ion implantation (244A) and in-situ doped epitaxial deposition (244B). Optionally, as shown in step 244C, PMOS or NMOS selective EPI layers can be formed in the source and drain regions as performance enhancers for strained channels. Source 212 and drain 214 can further include raised and/or recessed source/drains, asymmetrically doped, counter-doped or crystal structure modified source/drains, or implant doping of source/drain extension regions according to LDD (lightly doped drain) techniques, provided that the thermal budget for any anneal steps be within the boundaries of what is required to keep the screening region 226 and threshold voltage setting region 228 substantially intact.

In step 246, a metal gate is formed in accordance with a gate last process. Step 246 is optional and may be performed only for gate-last processes (246A).

Referring back to FIG. 2A, the channel 218 contacts and extends between the source 212 and the drain 214, and supports movement of mobile charge carriers between the source and the drain. In operation, when gate electrode voltage is applied to the DDC transistor 200 at a predetermined level, a depletion region formed in the substantially undoped channel 218 can extend to the screening region 226, since channel depletion depth is a function of the integrated charge from dopants in the doped channel lattice, and the substantially undoped channel 218 has very few dopants. The screening region 226, if fabricated according to specification, effectively pins the depletion region to define the depletion zone width.

As will also be appreciated, position, concentration, and thickness of the screening region 226 can be important factors in the design of the DDC transistor. In certain embodiments, the screening region 226 is located above the bottom of the source and drain junctions. A screening region 226 can be doped to cause a peak dopant concentration to define the edge of the depletion width when the transistor is turned on. Such a doping of a screening region 226 can include methods such as delta doping, broad dopant implants, or in-situ doping is preferred, since the screening region 226 should have a finite thickness to enable the screening region 226 to adequately screen the well below, while avoiding creating a path for excessive junction leakage. When transistors are configured to have such screening regions, the transistor can simultaneously have good threshold voltage matching, high output resistance, low junction leakage, good short channel effects, and still have an independently controllable body due to a strong body effect. In addition, multiple DDC transistors having different threshold voltages can be easily implemented by customizing the position, thickness, and dopant concentration of the threshold voltage set region 228 and/or the screening region 226 while at the same time achieving a reduction in the threshold voltage variation.

In one embodiment, the screening region is positioned such that the top surface of the screening region is located approximately at a distance of Lg/1.5 to Lg/5 below the gate (where Lg is the gate length). In one embodiment, the threshold voltage set region has a dopant concentration that is approximately 1/10 of the screening region dopant concentration. In certain embodiments, the threshold voltage set region is thin so that the combination of the threshold voltage set region and the screening region is located approximately within a distance of Lg/1.5 to Lg/5 below the gate.

Modifying threshold voltage by use of a threshold voltage set region 228 positioned above the screening region 226 and below the substantially undoped channel 218 is an alternative technique to conventional threshold voltage implants for adjusting threshold voltage. Care must be taken to prevent dopant migration into the substantially undoped channel 218, and use of low temperature anneals and anti-migration materials such as carbon or germanium can be included in embodiments. More information about the formation of the threshold voltage set region 228 and the DDC transistor is found in pending U.S. patent application Ser. No. 12/895,785 filed Sep. 30, 2010, the entirety of which disclosure is herein incorporated by reference.

Yet another technique for modifying threshold voltage relies on selection of a gate material having a suitable work function. The gate electrode 210 can be formed from conventional materials, preferably including, but not limited to, metals, metal alloys, metal nitrides and metal silicides, as well as laminates thereof and composites thereof. In certain embodiments the gate electrode 210 may also be formed from polysilicon, including, for example, highly doped polysilicon and polysilicon-germanium alloy. Metals or metal alloys may include those containing aluminum, titanium, tantalum, or nitrides thereof, including titanium containing compounds such as titanium nitride. Formation of the gate electrode 210 can include silicide methods, chemical vapor deposition methods and physical vapor deposition methods, such as, but not limited to, evaporative methods and sputtering methods. Typically, the gate electrode 210 has an overall thickness from about 1 to about 500 nanometers. In certain embodiments, metals having a work function intermediate between band edge and mid-gap can be selected. As discussed in pending U.S. patent application Ser. No. 12/960,266 filed Dec. 3, 2010, the entirety of which disclosure is herein incorporated by reference, such metal gates simplify swapping of PMOS and NMOS gate metals to allow a reduction in mask steps and different required metal types for systems on a chip or other die supporting multiple transistor types.

Applied bias to the screening region 226 is yet another technique for modifying threshold voltage of a DDC transistor 200. The screening region 226 sets the body effect for the transistor and allows for a higher body effect than is found in conventional FET technologies. For example, a body tap 230 to the screening region 226 of the DDC transistor can be formed in order to provide further control of threshold voltage. The applied bias can be either reverse or forward biased, and can result in significant changes to threshold voltage. Bias can be static or dynamic, and can be applied to isolated transistors, or to groups of transistors that share a common well. Biasing can be static to set threshold voltage at a fixed set point, or dynamic, to adjust to changes in transistor operating conditions or requirements. Various suitable biasing techniques are disclosed in pending U.S. patent application Ser. No. 12/708,497 filed Feb. 18, 2010, the entirety of which disclosure is herein incorporated by reference.

Advantageously, DDC transistors created in accordance with the foregoing embodiments, structures, and processes, can have a reduced mismatch arising from scattered or random dopant variations as compared to conventional MOS transistors. In certain embodiments, the reduced variation results from the adoption of structures such as the screening region, the optional threshold voltage set region, and the epitaxially grown channel region. In certain alternative embodiments, mismatch between DDC transistors can be reduced by implanting the screening layer across multiple DDC transistors before the creation of transistor isolation structures, and forming the channel layer as a blanket epitaxial layer that is grown before the creation of transistor epitaxial structures. In certain embodiments, the screening region has a substantially uniform concentration of dopants in a lateral plane. The DDC transistor can be formed using a semiconductor process having a thermal budget that allows for a reasonable throughput while managing the diffusivities of the dopants in the channel. Further examples of transistor structure and manufacture suitable for use in DDC transistors are disclosed in U.S. patent application Ser. No. 12/708,497 (previously mentioned above) as well as U.S. patent application Ser. No. 12/971,884, filed on Dec. 17, 2010 and U.S. patent application Ser. No. 12/971,955 filed on Dec. 17, 2010, the respective contents of which are incorporated by reference herein.

FIG. 3 shows a simplified small signal model of the DDC transistor, where the input signal Vin is applied to both the gate and the screening region of the DDC transistor, i.e., Vgs=Vbs=Vin. Under these conditions, the output voltage Vout is governed by the following equation:
Vout=(gm*Vgs+gmb*Vbs)*rout
Substituting Vgs=Vbs=Vin:
Vout=(gm*Vin+gmb*Vin)*rout=(gm+gmb)*rout*Vin=(gmeff*rout)*Vin
Therefore, a DDC transistor can have greater gain when the input signal is applied to both the gate and the screening region of the DDC transistor, because the effective transconductance of the DDC transistor (gmeff) is greater than the transconductance (gm) when the input signal is only applied to the gate. In addition, in one embodiment, the DDC transistor has a transconductance (gm) and output impedance (rout) that are greater than that of a conventional MOSFET, and therefore, the gain of the DDC transistor is increased as compared to a conventional MOSFET, as a result of applying the input signal to both the gate and the screening region of the DDC transistor.

FIG. 4 is a graph showing the relationship 432 between normalized Ids (drain to source current) and Vgs (gate to source voltage) for a DDC transistor when the input signal is applied to both the screening region and the gate terminals, in accordance with one embodiment. FIG. 4 also shows the relationship 434 for a conventional transistor when the input signal is applied to both body and gate terminals, and the relationship 436 for conventional transistor when the input signal is applied only to the gate terminal. The graphs shown in FIG. 4 were obtained from simulations performed on a DDC transistor and conventional transistor having one micron width and a one micron length, when the drain to source voltage is 0.5 volts. FIG. 4 shows that the DDC transistor with the input signal applied to both the screening region and the gate terminals, has a higher gain in the subthreshold mode, when compared to the conventional transistor.

FIG. 5A shows a schematic diagram of a current mirror 500 using DDC transistors, in accordance with one embodiment. Current mirror 500 can be one very particular implementation of the circuit shown in FIG. 1. A current mirror 500 can include two DDC transistors 502-0/1, bias circuit 504 and output current path 506. For DDC transistor 502-0, the gate (G), body (i.e., screening region) (B) and drain (D) terminals are connected together. For DDC transistor 502-1, the gate (G) and screening region (B) terminals are connected together. Sources (S) of DDC transistors 502-0/1 can be commonly connected to a low power supply voltage (VSS) via a current path 508.

A bias circuit 504 can include a current source 538 which can provide a reference current to Iin to a drain of DDC transistor 502-0. If the DDC transistor 502-1 and 502-0 have good matching of their electrical characteristics (such as channel length, width, threshold voltage, etc.), DDC transistor 502-1 can mirror DDC transistor 502-0 such that the output current Iout is about the same as Iin, or such devices can be scaled with respect to one another to provide an accurate multiplication of an input current.

FIG. 5B is a graph showing the relationship between the output current (labeled “Iout” in FIG. 5A) and the gate voltage (labeled “Vgate”), which is the voltage at the gate of transistor 502-0) of the current mirror 500, in accordance with one embodiment. The curve 505 shows the relationship between Iout and gate voltage for the current mirror embodiment shown in FIG. 5A, where the voltage signal at the gate terminal is also applied to the screening region terminal. The curve 507 shows the relationship between Iout and gate voltage for a current mirror embodiment that uses DDC transistors, but the screening region terminals of the DDC transistors 502-0/1 are connected to VSS instead of being connected to the gate, such that no voltage signal is applied to the screening region. FIG. 5B shows that the current mirror having the voltage signal applied to both the screening region and gate terminals can require a lower gate voltage to provide a predetermined current Iout compared to a current mirror with the voltage signal applied to the gate terminal only (i.e., with no voltage signal applied to the screening region terminal). For example, for the embodiments illustrated in FIG. 5, the gate voltage can be approximately 80 mV lower for the same current Iout, when the voltage signal is applied to both the screening region and gate terminals.

FIGS. 6A and 6B are schematic diagrams of operational transconductance amplifier (OTA) circuits 600-A/B incorporating DDC transistors, in accordance with certain embodiments. Such OTA circuits can be particular implementation of the circuit shown in FIG. 1.

Referring to FIG. 6A, an OTA circuit 600-A can include a pair of input DDC transistors 602-0/1, a bias circuit 604, and a current path bias circuit 608. A bias circuit 604 can include current mirror P60/P62 connected to the drain of DDC transistor 602-0, and a current mirror P64/P66 connected to a drain of transistor 602-1. Bodies of p-channel transistors P60/P62/P64/P66 can be connected to a high power supply voltage (VDD). Transistor P66 can serve as a pull-up portion of an output stage that drives output 652. In one embodiment, transistors P60/P62/P64/P66 can be DDC transistors and thus have screening regions connected to VDD.

DDC transistors 602-0/1 can form a differential pair. DDC transistor 602-0 can have a gate connected to a first input 650-0 and a drain connected to current mirror P60/P62. DDC transistor 602-1 can have a gate connected to a second input 650-1 and a drain connected to current mirror P64/P66. Sources and bodies (i.e., screening regions) of DDC transistors 602-0/1 can be commonly connected to a bias node 653.

Current path bias circuit 608 can include current mirror N60/N64, which can provide a bias current to differential pair 602-0/1 based on a reference current Ibias from a current source 654. Bias circuit 608 also includes current mirror N62/N66, which can serve as an active load to current mirrors P60/P6 and P64/P66, respectively. Transistor N66 can serve as an output load for the output 652. In one embodiment, transistors N60/N62/N64/N66 can be DDC transistors and thus have screening regions connected to VSS.

Referring to FIG. 6B, an OTA circuit 600-A can include a structure like that of FIG. 6A, however, screening regions of transistors can be connected to their corresponding gates. Accordingly, bodies (and hence screening regions) of input DDC transistors 602-0′/1′ can be connected to their respective gates.

In one embodiment, transistors P60′/P62′/P64′/P66′ can be DDC transistors and thus have screening regions connected to their corresponding gates. In addition or alternatively, transistors N60′/N62′/N64′/N66′ can have their screening regions connected to their gates.

In the embodiments of FIGS. 6A and 6B, a reference current Ibias can be selected to ensure that all DDC transistors operate in the sub-threshold mode. In such an embodiment, transistors can provide greater current gain at lower gate voltages, thus a power supply voltage can be lower than op amps constructed of conventional transistors. In some embodiments a power supply voltage (i.e., VDD-VSS) can be 0.5 volts. In alternative embodiments, a power supply voltage can be less than 0.5 volts.

FIGS. 7A to 7D are graphs showing operating characteristics of the OTA circuits of FIGS. 6A and 6B at various power supply voltages (VDD). FIG. 7A compares the gain 758 of an OTA circuit like that of FIG. 6A with DDC transistors (hereinafter referred to “gate only”) and the gain 756 of an OTA circuit like that of FIG. 6B with DDC transistors (hereinafter referred to as “gate and screen”). FIG. 7B compares a phase margin of the gate only configuration 762 with that of a gate and screen configuration 760. FIG. 7C compares a unity gain frequency of a gate only configuration 766 with that of a gate and screen configuration 764. FIG. 7D compares power consumption of a gate only configuration 770 with that of a gate and screen configuration 768.

The graphs illustrated in FIGS. 7A to 7D were obtained from AC simulation of the OTA circuits of FIGS. 6A and 6B (with all DDC transistors) with a 1 pF capacitor load on the output terminal 652. The graphs in FIGS. 7A to 7D illustrate that the OTA circuit 600-B having the signal applied to both the gate and the screening region terminals has enhanced performance (as illustrated by curves 756, 760, 764, and 768) for the same power and can provide a higher gain and operate at a lower value of supply voltage VDD as compared to the gate only OTA circuit configuration (as illustrated by curves 758, 762, 766, and 770).

FIG. 8 is a table illustrating simulation results obtained from simulations performed on an OTA circuit using DDC transistors and having the gate and screening region terminals connected together (as in FIG. 6B), and an OTA circuit using conventional transistors, in accordance with one embodiment. The simulation results were obtained for a power supply voltage of 0.5 volts. The OTA circuit using DDC transistors has enhanced performance characteristics, at least in part, due to the enhanced output resistance and the enhance effective transconductance of the DDC transistor.

FIG. 9 is a schematic diagram of an operational amplifier 900 using DDC transistors according to a further embodiment. An op amp circuit 900 can include a pair of input DDC transistors 902-0/1, a bias circuit 904, and a current path bias circuit 908. A bias circuit 904 can include current mirror formed by p-channel DDC transistors P92/P94 with drains connected to the drains of DDC transistors 902-0/1, resistor R90, capacitance C90 and an output p-channel DDC transistor P96. P-channel DDC transistors P92/P94/P96 can have bodies (i.e., screening regions) connected to their gates, and sources connected to power supply VDD.

DDC transistors 902-0/1 can form a differential pair, and have their gates connected to the bodies (i.e., screening regions), and sources connected to common node 953.

Current bias circuit 908 can include current mirror formed by n-channel DDC transistors N90/N94, a current source 954, and output n-channel DDC transistor N96. Current mirror circuit N90/N94 can provide a bias current to differential pair 902-0/1 based on a reference current Ibias from a current source 954. Bias circuit 908 also includes current mirror N62/N66, which can serve as an active load to current mirrors P60/P6 and P64/P66, respectively. Transistor N66 can serve as an output load for the output 952. Sources of DDC transistors N90/N94/N96 can be connected to a low power supply VSS.

Referring still to FIG. 9, an input signal can be connected to input terminals 950-0/1, and thus to the gate and screening region terminals of the 902-0/1. An amplified output voltage (Vout) can appear on output node 952.

In one embodiment, a power supply voltage (VDD) can be 0.5 volts and a lower power supply voltage (VSS) can be 0 volts. In alternative embodiments, a power supply voltage (VDD) can be less than 0.5 volts and a lower power supply voltage (VSS) can be 0 volts.

DDC transistors configured to receive an input signal at both the gate terminal and the screening region terminal can also be used in digital circuit configurations.

Such embodiments using DDC transistors can include inverters, NAND gates, and NOR gates. In one embodiment, one or more transistors in a digital circuit configuration can be a DDC transistor configured to receive an input signal at both a gate terminal and the screening region terminal. Such embodiments can be capable of sub-threshold operation. In one embodiment, such digital circuits can operate at power supply voltages less than 0.5 volts. In an alternative embodiment, such digital circuits can operate at a power supply voltage of approximately 0.3 volts. In one embodiment of such circuits having a digital configuration, the parasitic BJT current is very small and the digital circuit can have reduced likelihood of latch-up (greater latch-up resistance or avoidance) at low power supply voltages (as low as 0.3 volts) because the forward bias in the PN-junctions may not be sufficient to generate a significant current in these circuits.

FIGS. 10A and 10B are schematic diagrams of five stage ring oscillators that are implemented with DDC transistors, in accordance with embodiments. FIG. 10A shows a ring oscillator 1000-A having five stages 1070-0 to -4, with each stage including a p-channel DDC transistor P100 and an n-channel DDC transistor connected in a CMOS inverter type configuration. P-channel DDC transistors P100 can have bodies (i.e., screening regions) connected to a high power supply voltage VDD, while n-channel DDC transistors N100 can have bodies (i.e., screening regions) connected to a low power supply voltage VSS.

FIG. 10B shows a ring oscillator 1000-B having five stages 1070-0′ to -4′ like that of FIG. 10A. However, in FIG. 10B, n-channel and p-channel DDC transistors P100′/N100′ can have bodies (i.e., screening regions) connected to their respective gates.

FIG. 10C is a diagram showing two oscillator stages 1070-0/1 in side cross sectional views. FIG. 10C shows how connecting gate and screening region to one another can produce an equivalent circuit to a gate-only circuit (e.g., the circuit of FIG. 10A) in parallel with a parasitic bipolar version of the circuit. Similar to the embodiments discussed above, connecting the gate and screening region terminals of the DDC transistors can increase the effective transconductance of the DDC transistor resulting in circuits in digital configurations that operate at a higher speed operation at a given power supply voltage than circuits with conventional transistors having conventional terminal connections.

FIG. 11 is a table summarizing the speed and power of the five stage ring oscillator illustrated in FIG. 10A (columns labeled “Gate-only”) and FIG. 10B (columns labeled “Gate and Screen”). The speed for the ring oscillator of FIG. 10B can be up to 4 times faster than that of the ring oscillator of FIG. 10A, at VDD=0.3 V. In certain embodiments, the power supply voltage of the ring oscillator of FIG. 10B can be reduced to voltages as low as about 0.25 V to achieve the same speed as the ring oscillator of FIG. 10A operating at a higher power supply voltage.

While embodiments have shown circuits with DDC transistors as active circuit elements, other embodiments can employ such structures to realize passive circuit elements. In particular embodiments, DDC transistors can be used in variable capacitance (e.g., varactor) type circuits. Embodiments can include varactor circuits with DDC transistors having an enhanced body coefficient. Particular embodiments of the method and techniques described herein may be applicable to integrated circuits that include ring oscillators, and voltage controlled oscillators.

FIG. 12 shows a DDC transistor 1202 configured as an inversion mode MOS-type (I-MOS) varactor (hereafter referred to as “DDC I-MOS varactor”) configured to operate in a test circuit 1200, according to an embodiment. A DDC I-MOS varactor 1202 has an enhanced capacitance tuning range arising from the enhanced body coefficient and smaller threshold voltage variation of the DDC transistor.

FIGS. 13A and 13B illustrate graphs of capacitance as a function of the gate voltage (hereinafter referred to as “C-V curves”) showing the enhanced capacitance tuning range of the DDC I-MOS varactor 1202, in accordance with embodiments.

The C-V curves shown in FIG. 13A are small signal analysis results obtained from simulations performed with the test circuit 1200 using a DDC I-MOS varactor as described herein. Tests included sweeping the gate bias voltage, V_G, with four different bias combinations for V_SDand V_B.

The C-V curves shown in FIG. 13B are simulation results corresponding to those of FIG. 13A, but with conventional MOS transistor based I-MOS varactor.

The four bias conditions used in FIGS. 13A and 13B are (i) V_SD=0 volts and V_B=0.45 volts, (ii) V_SD=0.45 volts and V_B=0 volts, (iii) V_SD=0 volts and V_B=0 volts, and (iv) V_SD=0.45 volts and V_B=0.45 volts. The frequency of the test signal V_acwas 500 MHz for the simulation results shown in FIGS. 13A and 13B. In one embodiment, the bias voltage V_Bis applied to the screening region of the DDC transistor used to implement the DDC I-MOS varactor 1202.

FIG. 13A illustrates that in addition to the voltage V_SD, the voltage V_Bcan also be used to increase the capacitance tuning range of the DDC I-MOS varactor 1202. FIG. 13A includes arrow labeled “vb”, which shows a capacitance shift corresponding to changes in a body voltage V_B(i.e., screening region bias), and arrow labeled “vsd”, which shows a capacitance shift corresponding to changes in a source-drain voltage (V_SD) As shown, a greater shift occurs with V_SDthan with V_Bfor the same amount of voltage change (0.45 V). Further, the C-V curves shift in opposite directions for V_SDand V_Bbias voltages. In one embodiment, the widest capacitance tuning range can be obtained by changing the bias voltages V_SDand V_Bin opposite directions (i.e., in the very particular conditions of FIG. 13A, by changing the bias voltage V_SDfrom 0V to 0.45V, while the bias voltage V_Bis changed from 0.45V to 0V). In one embodiment, the capacitance tuning range of the DDC I-MOS varactor 1202 can be enhanced by approximately 30%, as a result of applying the bias voltage V_SDand V_Bas described.

FIG. 13B includes corresponding arrows labeled “vb” and “vsd” showing capacitance shifts for a conventional I-MOS varactor. As shown by comparing FIGS. 13A and 13B, the DDC I-MOS varactor has an enhanced capacitance tuning range as the bias voltages V_SDand V_Bare changed as compared to the corresponding capacitance tuning range of conventional I-MOS varactor.

FIG. 14A illustrates a varactor circuit 1400 according to an embodiment in a block schematic diagram. A varactor circuit 1400 can apply differential bias voltages V_SDand V_Bto extend the capacitance tuning range of DDC I-MOS varactors 1402′, in accordance with one embodiment.

As understood with reference to FIGS. 12, 13A and 13B, discussed above, the overall tuning range can be extended by applying capacitance tuning bias voltages to V_SDand V_Bdifferentially. The circuit 1400 can include current sources 1456-0/1, resistors R140, R142, R144, p-channel transistors P140/P142, capacitances C140/C142 and DDC transistors 1402-0/1 configured in parallel as a capacitance element 1402. In one embodiment, transistors P140/P142 can be DDC transistors.

Current source 1456-0 can provide a bias current to a source of p-channel transistor P140, and current source 1456-1 can provide a bias current to a source of p-channel transistor P142. Resistance R140 can be connected between sources of transistors P140/P142. Transistor P140 can receive a bias control voltage (Vcont) at its gate, which in the very particular embodiment shown, can vary between 0 V and 0.5 V. A gate of transistor P142 can receive a bias voltage midway between that applied to the gate of P140 (which is 0.25 V in the embodiment shown). Resistance R142 and capacitance C142 can be connected between a drain of P140 and a low power supply VSS. Similarly, resistance R144 and capacitance C140 can be connected between a drain of P142 and low power supply VSS. Resistances R142 and R144 can be the same. Capacitances C140 and C142 can be the same.

DDC transistors 1402-0/1 can have source/drains commonly connected to a drain of transistor P142. Bodies (i.e., screening regions) of DDC transistors 1402-0/1 can be commonly connected to a drain of transistor P140. DDC transistors 1402-0/1 can form a capacitance element 1402 between nodes V_GAand V_G2.

Varactor circuit 1400 can present a single-to-differential gain stage with the gain defined by 2*R142/R140. By adjusting the ratio of the resistors R142/R144 and R140, the rate of change for the bias voltages applied to nodes V_SDand V_Bcan be adjusted and the desired differential voltage swing can be developed between these two bias voltages. As shown by waveforms V_Band V_SD, in operation, bodies of DDC transistors 1402-0/1 will receive a voltage V_Bthat varies in an opposite manner to that applied to source drains (V_SD).

As understood from FIG. 13A, DDC I-MOS varactors 1402-0/1 application of opposing V_SDand V_Bpotentials can improve a quality factor Q of an oscillating circuit incorporating such varactors. Simulation results obtained from this differential biasing circuit 1400 show that a DDC I-MOS varactor can have a capacitance tuning range that is enhanced by as much as 45% compared to a conventional I-MOS varactor that uses a conventional MOS transistor and only one bias voltage V_SD.

FIG. 14B shows an equivalent representation of capacitance element 1402 shown in FIG. 14A. By varying control signal (Vcont), a capacitance between nodes V_G1and V_G2can be varied.

FIG. 15A illustrates a ring oscillator-type voltage controlled oscillator (VCO) 1500 that uses DDC varactor circuits as capacitive load elements in accordance with one embodiment. The VCO 1500 includes a voltage-to-current (V-I) converter (or a regulator) 1556 that provides a current I_OSCto a current controlled ring oscillator (CCO) 1558. A CCO 1558 can include a number of stages (three shown as 1570-0 to -2) arranged in series with one another. A DDC I-MOS varactor can be connected as a load capacitance to one or more outputs of such stages. The very particular embodiment of FIG. 15 shows a DDC I-MOS varactor (1502-0 to -2) at outputs of each stage (1570-0 to -2). A voltage control signal V_CONTcan be used to set a coarse frequency for CCO 1558. A fine frequency control can be done through varactor tuning by changing the bias voltages (V_Band V_SD) applied to the varactors via voltage sources 1558-0/1. In alternative embodiments, where the bias voltages (V_Band V_SD) are generated by a single-to-differential gain stage, as illustrated in FIG. 14A, that applies differential bias voltages V_Band V_SDbased on a bias control voltage, the varactor tuning can be changing the bias control voltage applied to the single-to-differential-gain stage.

In one embodiment, any or all of oscillator stages (e.g., 1570-0 to -2) can be formed from DDC transistors, such as those shown in FIG. 10A or 10B.

In one particular embodiment, a VCO 1500 can be used as part of a Clock and Data Recovery (CDR) circuit.

FIG. 15B illustrates an alternative embodiment of a ring oscillator 1500′ using differential delay element stages and DDC varactor circuits. The VCO 1500 includes differential delay elements (1572-0 to 3), where each stage has a non-inverting output (OUT) and an inverting output (OUTN). The differential delay element can be implemented using inverters 1520, 1522, 1524, and 1526 as illustrated in the figure. A DDC I-MOS varactor can be connected as a load capacitance to one or more outputs of such delay element stages. The very particular embodiment of FIG. 15B shows a DDC I-MOS varactor (1504 and 1506) coupled between the non-inverting and inverting outputs (i.e., between OUT and OUTN) of each delay element stage (1572-0 to -3). The frequency control of the ring oscillator 1500′ can be done through varactor tuning by changing the bias voltages (V_Band V_SD) applied to the varactors via voltage sources 1558′-0/1. In alternative embodiments, where the bias voltages (V_Band V_SD) are generated by a single-to-differential gain stage as illustrated in FIG. 14A that applies differential bias voltages V_Band V_SDbased on a bias control voltage, the varactor tuning can be changing the bias control voltage applied to the single-to-differential-gain stage.

In one embodiment, any or all of oscillator stages (e.g., 1572-0 to -3) can be formed from DDC transistors, such as those shown in FIG. 10A or 10B.

In one particular embodiment, a ring oscillator 1500′ can be used as part of a Clock and Data Recovery (CDR) circuit.

FIG. 16A illustrates the C-V curves of a DDC I-MOS varactor for various values of bias voltage V_SDand the resulting average capacitive load at the output node of a CCO stage, like that of FIG. 15A, in accordance with one embodiment. As described above, the bias voltages (V_Band V_SD) can have an impact on the flat-band voltage of the DDC I-MOS varactor resulting in the shift of C-V curves as the MOS capacitor inversion point is changed.

As shown in FIG. 16A, the time domain waveforms of ring oscillator VCO (e.g., 1500) can behave like a pulse modulated signal as the signal oscillates up and down at each stage of the CCO 1558. In FIG. 16A, the oscillator stage output large signal time domain behavior 1662 is superimposed on the DDC I-MOS varactor C-V characteristics, to produce pulse shape time domain capacitance curves 1664 as shown in FIG. 16A. For the embodiment illustrated in FIG. 16A, the body bias voltage V_B=0 and the oscillation amplitude is 0.6 V. As illustrated in FIG. 16A, when this 0.6 V amplitude oscillating signal is applied to the DDC I-MOS varactor having the C-V curve shown for V_SD=0, the corresponding capacitance curve 1664-0 will have higher amplitude as compared to the capacitance curve for V_SD=0.5 V 1664-1. Therefore, the DDC I-MOS varactor has a higher average capacitance value for V_SD=0, and average capacitance value decreases with increasing bias voltage V_SD(e.g., the average capacitance is 2.45 pF for V_SD=0, 1.45 pF for V_SD=0.5).

FIG. 16B illustrates plots of the average capacitance versus V_SDas the oscillation amplitude is varied from 0.4 V to 0.8 V, in accordance with one embodiment. In alternate embodiments, increased variation of the average capacitance, i.e., increased capacitance tuning, can be obtained by changing the bias voltage V_Bin addition to changing V_SD, as would be understood from FIG. 13A.

FIG. 17 illustrates a graph of the average capacitance of the DDC I-MOS varactor, and a conventional MOS varactor as a function of the signal amplitude of a VCO (e.g., 1500) as the bias voltages V_SDand V_Bare changed between 0 volts and 0.45 volts. FIG. 17 illustrates that the DDC I-MOS varactor has an enhanced tuning range for the average capacitance as compared to the conventional I-MOS varactor. FIG. 17 shows that the average capacitance tuning range for the DDC I-MOS varactor becomes increasingly wider as the ring oscillator signal swing amplitude increases.

FIG. 18 is a schematic diagram for an LC-type VCO 1800 using DDC I-MOS varactors, in accordance with one embodiment. Since the common mode voltage of the LC VCO is biased at the power supply voltage VDD, the tuning range of the varactors in the LC VCO can be different from the tuning range of varactors in a ring oscillator VCO, such as that shown in FIGS. 15A and 15B.

In the embodiment shown, an LC-type VCO 1800 can include a varactor element 1802, inductors L180/L182, capacitances C180/C182, n-channel transistors N180/N182, and current source 1866. Varactor element 1802 can have a structure like that of FIG. 14A, having source-drain connections that can be biased with a voltage V_SD, and bodies (i.e., screening regions) that can be biased with a voltage V_B. Varactor element 1802 can be connected between oscillation nodes 1868-0/1.

Inductor L180 can be connected between a supply node VDD and oscillation node 1868-0, while inductor L182 can be connected between supply node VDD and oscillation node 1868-1. A load capacitance C180 can exist between oscillation node 1868-0 and a low supply node VSS, while a load capacitance C182 can exist between oscillation node 1868-1 and low supply node VSS.

Transistors N180/N182 can be cross-coupled between nodes 1868-0/1, each transistor having its gate connected to the other's drain. Sources of transistors N180/N182 can be connected to current source 1866. Current source 1866 can provide a bias current I_T.

FIG. 19 illustrates the C-V curves of a DDC I-MOS varactor for various values of bias voltage V_SDand resulting average capacitive load for a single cycle of the LC VCO 1800, in accordance with one embodiment. In the embodiment of FIG. 19, an oscillating signal 1972 having an amplitude of 0.6 volts (1.2 volts peak-to-peak) is applied to the C-V curves to obtain the average capacitance C_AVG. In FIG. 19, the average capacitance values for the DDC I-MOS varactor in the LC VCO circuit are shifted to higher values than the ring oscillator VCO shown in FIG. 16A, (i.e., 1.6 pF to 3.8 pF) because a higher gate voltage is applied to the DDC I-MOS varactors in the LC VCO circuit 1800.

FIG. 20 illustrates graphs of the average capacitance of the DDC I-MOS varactor, and a conventional MOS varactor as a function of the LC VCO signal amplitude as the bias voltages V_SDand V_Bare changed between 0 volts and 0.45 volts. FIG. 20 illustrates that the DDC I-MOS varactor has an enhanced tuning range for the average capacitance in comparison to the average capacitance tuning range for the conventional MOS varactor.

FIG. 21 is a graph illustrating the enhancement of a tuning range for the DDC I-MOS varactor with respect to a conventional MOS varactor as a function of the LC VCO signal amplitude, in accordance with one embodiment. FIG. 21 illustrates that the DDC I-MOS varactor has a tuning range that is at least 45% greater than the conventional MOS varactor.

It should be appreciated that in the foregoing description of exemplary embodiments of the invention, various features of the invention are sometimes grouped together in a single embodiment, figure, or description thereof for the purpose of streamlining the disclosure aiding in the understanding of one or more of the various inventive aspects. This method of disclosure, however, is not to be interpreted as reflecting an intention that the claimed invention requires more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive aspects lie in less than all features of a single foregoing disclosed embodiment. Thus, the claims following the detailed description are hereby expressly incorporated into this detailed description, with each claim standing on its own as a separate embodiment of this invention.

It is also understood that the embodiments of the invention may be practiced in the absence of an element and/or step not specifically disclosed. That is, an inventive feature of the invention may be elimination of an element.

Accordingly, while the various aspects of the particular embodiments set forth herein have been described in detail, the present invention could be subject to various changes, substitutions, and alterations without departing from the spirit and scope of the invention.