[1]United States Patent Office 393722310 3,372,310 UNIVERSAL MODULAR PACKAGES FOR INTEGRATED CIRCUITS Misha Kantor, Orlando, Fla., a-esignor to Radiation 5 Incorporated, Melbourne, Fla., a corporation of Florida Filed Apr. 30, 1965, Ser. No. 452,184 5 Claims. (Cl. 317-101) 1,9 The present invention relates generally to the field of microelectronics, that is, to the p.,cduction of microminiaturized electronic structures, and more particularly to modular packages of integraled circuits arranged in planar or multiplanar array to form electronic subsysteras or 15 systems, and to processes for mantifacturi@-ig the inte.@rated circuit modules. A@nong the several objects of the present inventic>n, the following are of primary importance: (1) To provide planar module,, of integrated physical 20 and electrical strL7cture in environmentally st,-,b-le packages; (2) To provide maximlm,density packa.@in.- of microelectronic cornponents with a high degr,-e of reliability in overall circuit operation; 25 (3) To reduce the cost of manufactise of integrated circuits by e@lectrically interconnecting uncased moliolithic chips, that is, microcleelronic and thin fi@im inte,,@- rated devices, via an intraconnected matrix oi. condlictors applied to the support slibstrate of a universal niodule 30 to which,the chips are integrally bonded; (4) To provide processes for production of pla-@lar modL,Ies @vhich will redlice loss of material or scrap factor to mirimum levels; (5) To provide planar modules v;hiel-i are protected 35 against internal damage from shock and vibration; (6) To provide improved methods and ineans of connectin.@ the circuit chips to the conductive matrix of the module; (7) To redtice the stresses on cornections and inter 40 connections witliin the integrated circuit module by elimination of any necessity of physical support or restraint of the chips by the co@inections; To provide abrasion-resistant and radiation-resistant microelectronic packages; 45 (9) To provide modular packages of plug-in construction wherein the coniiector pins of each package are integral with the matrix of conductors traversing the module substratc; (10) To provide a matrix of conductors within the 60 base substrate wherein the cop@ductors are interconnected via a pattern of conductor-carryin.- through holes. The problems which hav@- been heretofore ericountered in the production of microel-@ctronic circuit striieture are many. Two of the more serious are, first, that techniqiies 55 adapted to the fabrication of conventionally-sized (according to former standards) component packages are unsliit,ible for the production of rnicroelectronic packages. Basically, this problem arises from the vast differences in the suitability of connections between circui" components and 60 conductive leads, and in the matiner and facility of component ipounting in the two types of packages. Secondly, prior art microelectronic structures have been plagiied by far lower eircliit reliability tiian that which has b,--.n achieved using conventionally-size el.-etronic packages. 65 The so-orce of this problem lies in both electrical a@ld physical difficulties stemrnin.- to a great extent from the vast reduction in size of !ih@- former over the latter, although other considerations, such as appropri,,lteness of materials, are also involved. T'no present invention is intended to solve these and other significant p@-oblenis in the field of microelectronics. Patented Mar. 5, 1968 2 Briefly, in accordance with the present invention, a planar integrated circuit module comprises a plurality of microelectronic circuit cbips, a substrate for supportin@a the chips integrally therewith in a predetermined array )iid having pliysical and r,Iectrical properties su-bstantially identical to those of the chip substrate, an intraconnected matrix of co-nductors lacing the substrate, selected ones of tlae leads or lands of the chiprnicrocircuits bein- con0 necled to selected ones of the co,,iductors in the matrix, a plurality ol. connector pias partially mclded in the body of th.- stibstrate and projecting fror@i a surface thereof, the pins being integral witli selected conductors of the matrix respeelively, a spacer layer of substrate rqaterial over 'the support or base and chips, a pair of irsulatively coated retal cover plates between which the substrate, chips and spacer are iiiterposed, means - providing a heTmetic seal of the entire arra-Ti@emeDt of component parts, and @a protective shock and 'vibration resistant band or ftame vvrapped about the ends of the assembly to prevent internal damage to the module. Also, bi-iefly stated, a process for producirg pla-,iar modul--s of the above described typ,- iri accordance with the present invention comprises the steps of molding the substrate with a - predetermined array of connector pins extending partially internally tliereaf, and wilh a pattern of spac,-d grooves along surfaces of the substrate in accordaqcc with the desired matrix pattern of conductors to be deposited therein, providing a plurality of holles through the substrate to connect variotis grooves at crossover points on opposite surfaces, depositing conductive Piaterial in the grooves and holes to provide the desired conductor matrix, surface grinding both sides of the substrate to reinove und,-sired conductive material from areas betwcen the grooves, dipping and glazing the sLbstrate to protect t,ie conductors, positioning ihe microelectronic circliit cbips i.-i place at surf-aoe re.-ions of the substrate between conductors @nd thermally bonding the chips in aii integral r--Iaiionship with the substrate, removing condtictive n-iaterial from the grooves at predetermined poin-ts of the matrix to provide the desired circuit tcrminations after the chips are interconnected via the rnatrix, placing a spacer layer of substrate material over the circuit chips aid applying cover plates to the exterior surfaces of substrate and spacer layer, hermetically sealin the ass.-inbly, and @vtapping a resilient band of metallic rriaterial about the edges of the assembly to provide shock aiid vibration resistance. In addition tc) the objectives and advantages of the -planar module aiid the fabr;cation process previolisly mentioned, the structure of the modules is so developed as to be par,icularly adaptable to fabrication by computerized eirciiit design and analysis techniques as well as by other forms of automaled asse@iibly so that ir@ass productioi of the modules is readily effected. Moreover, large quantities o'L universal or standardized modules may be produced preparatory to tlle manufacture of fir@al inte.-rated circuit packages therefrom, and independently of any knowledge of final circuit requii-ements. This feature of adaptability to virttially any circuit desig-@i requirement is provided by the integrated constrtiction cf stipport substrate, intraconnected conductive malrix, and external circait connectin.- @points integral with the matrix. Variations in flnal packaged circuitry will depend solely upon number and type of micrioelectronic circuit chips selected, upon the interconnection of the chips via the matrix, and upo-@i the voints of the matrix s,- Iccted for severance to establish th@d,,-sired circuit torminations. While this universality or unrestfioled versatility of the 70 basic modtile is extremely desirable and offers distinct production aivantages, it is to some extent collateral to other objects of the present invention. The invention con-
[2]3 te,mplates a p@hysical realization of multiple microcircuit elemen,ts which are inseparably associated both pbysically and electrically within a unitary or continuous body to perform the functions of a complete electronic system or a part thereof. Operational reliability of such units is extremely hi-h because of structural continuity in every aspect; yet@each unit may readily be replaced, in accoi.-daiice with chan.-ing system requirements or in the uiilikely event of unpredicted failure, by virtue of the plu@-in constr-ucion. In this connection, it will be noted thit system reliability may be evaluated from a knowledge of faflure rates of the components andinterconnections, althoL7gh a determination of failure rate is meanin.-ful onlv when accompanied by a knowledge of environmental coiiditions. When similar conditions exist, comparison of fail ure rates is valid; otherwise, extrapolation is required from available data. It will readily be appreciated that an inventory of on-hand units is maintained in accordance with predictable probability of system survival, and that, in conjunction therewith, it is most desirable to provide system components capable of rapid replacement to prevent lengthy down-times as well as to facilitate versatility of modification as a function of varying system requirements. The above and still further objects, feautres and attendant advantages of the present invention will become apparent upon a consideration of the following detailed description of specific embodiments thereof and specific processes of production, especially when taken in cor.- junction with the accompanying drawings in which: FIGURE 1 is a perspective view of an ecemplary form of the completed planar module; FIGURE 2 is an exploded view in perspective, showing some of the basic parts of the completed assembly; FIGURE 3 is a sectional view of the completed planar module taken through the lines 3-3 of FIGURE 1; FIGURE 4 is a fragmentary perspective view of the substrate of the module showing the interconnection of connecting pins and portions of the conductor matrix; FIGURE 5 is a fragmentary perspective view of a portion of the module showing one forni of cbip installation on the substrate and the electrical connection of the chip with the conductor matrix; FIGURE 6 shows another form of chip instahation and connection in fragmentary perspective view; FIGURE 7 shows still another form of chip installation and connection in fragmentary perspective view; and FIGURE 8 is a flow diagram illustrating the steps in an exemplary -process for producing planar integrated circuit modules. Referring now to the drawing wherein like reference numerals are used to refer to like parts in the several figures, the supporting substrate for the microelectronic circuit chips is selected from a material possessing physical and electrical properties corresponding closely to those of the chips, so that -,vhen the chips are bonded to the substrate, as will presently be described in detail, a truly inte-rated body of substrate and multiple circuit elements will be formed. Such an arrangement will eventually provide an electronic system or subsystem of inseparably associated components within a single continuous medium. It is desirable that the material of which the substrate is comprised be readilymoldable,,such as by transfer, injection, or compression molding or other conventional molding processes, into a grooved planar form. Moldable ceramics are presently available which nearly match the physicE(I and electrical characteristics of the monolithic substrate layer on which the microcircuits are disposed in the form of thin films or other integrated device stnicture of which the chips are comprised. A preferred material for the substrate is glass boiided mica compound, this material being especially compatible with system requirements. Moreover, the glass bonded mica, sold under the name "Mykroy," is particularly adaptable to conventional molding techniques and when hardened is readily machina-ble, as by grinding, drilling 3)372;310 4 and so fortb. The general and specific properties of several grades of Mykroy set forth in the table below illustrate its particular suitability for use as the supporl,in,@ substrate ii the planar module. 5 TABLE.-'%IYKROY PROPERTIES Glass-Bonded Mica Grades Properties Units AIykroy Mykroy Alykroy 10 750 1100 1116 General: Speoific Gravity ---------- ----------- 3.3 3.2 3.2 M.isture Absorption- ---. ----------- Nil Nil Nil Max. Continuous Temp - - - F -------- 750 1100 1100 Coef. of Expaiision ------- XIO-5, I F5.6 5.2 5.2 Electrical: 15 Vol. Resistivity ---------- ohm-cm--- 1013 1014 1014 Dielectric 1/g -------------- volts/mil-- 350 400 400 Dielectric CoTistant ------ I me ------ 7.1 7.50 7.4 Dissipation Factor. ------- I me ------ .0014 .0012 .0019 Loss Factor --------------- I me ------ .0099 .016 .014 Surface Res@.stiv@ty ------- Dry ohii-- 1016 1016 jolo Surface Resistivity ------- Wet ohm 1010 1011 1012 20 Mechanical: Tensile ------------------- p.s.i ------- 9,000 8,000 7,500 Flexural ------------------ p.s.i ------- 21,600 13,900 11,000 Cornpressive -------------- p.s.i ------- 36,000 30,000 30,000 Modulus of Elasticity ----- p.s.i ------- loxio6 7XIOG 7XI06 Impact Strength (Izod) --- in.-lbs ----- 1.7 1.3 1.2 25 In addition, Mykroy is an excellent insulator at high frequencies; it is capable of being molded with metal inserts or leads to extremely close tolerances; it is, like ceramic, dimensionally stable with changes of tempera30 ture, time and environment, but, unlike ceramic, it has a coefficient of thermal expansion close to that of most metals; it is readily machinable; it may be surfac-e ground to optical flatness, so that po-lishin- to a three microinch finish is attainable; it is adaptable to conventional 35 molding tecbniqu.-s so that it provides a means for production standardization and for the construction of bodies of various sihapes; and it is readily adaptable to any form of metalization, such as vacuum deposition and elect@roless plating as well as low-temperature fired-on metalizin@ 40 An exemplary process of producing the integrated circuit moduiles is best followed by reference to FIGURE 8 with conciirrent reference to the various figures showing d-etails of construction. Initially the substrate material is molded, such as by 45 compression, injection, or transfer moldidg, for example, to form an insulating sheet, slice, or slab 14 having a pair of opposed and spaced surfaces, with one of the surfaces containin-. a number of rows 16 of grooves 18 and the other surface a number of columns 21 of grooves 50 23 (see, e.g., FIGURE 5). That is, the rows and columns of grooves on opposite surfaces of the substrate r@un at substantially 90' to one another, but each surface contains only grooves r-unning in parallel alignment. In a preferred arrangem@nt, the grooves are placed in groups 55 of several spaced grooves each so that the groups are separated by a distance sufficient to allow the positioning of microelectronic circuit chips therebetween. Groove width and depth,dimensions of from .005 to .010 inch are readily attainable in the molding process of the glass 60 bonded mica substrate. It is contemplated that each planar integrated circuit 10 (FIGURES 1-3) will form an electronic system or subsystem which may be interconnected with various other modulles to form the desired complete electronic 65 assembly. The most advantageous arrangement, therefore, is that each module constitute a plug-in unithaving male connecting pins arranged to mate with female connectors, for example, in a system connecting board or package. To this end, a plurality of co-nnector pins or 70 other electrical connectors or terminals 25, suitable for establishing extemal circuit connection points are incorporated within the body of the substrate during the molding process in accordance with the preestablished array of mating connectors into which the moduie is to be 75 plugged. For this purpose, the substrate may include a
[3]8)872)3io 5 stepped port;oii 28 (FIGURE 4) along oiie surface 27 thereof and ad@jacent the end or edge 30 into which tihe internal conductors of the co-,inecting pins extend to the surface of the step. The external portions of pins 25 are arranged to project frorn the end surface of the substrate in a parallel array. Internally o@@' the substrate, the pins may comprise extended st.-ip conductors 34 which are arranged in any suitable manner to conform to the pattern of grooves on one or both of the substrate surfaces 27 and 36. It is desirable that 'Lhe cross sectional area of each pin and internal extended strip portion conform closely to the cross sectional area of each copductor of the matrix which is to be formed on the .main pilaiiar surfaces 27, 36 of the slabst@-ate. Following the step of molding the base or support substrate a matrix of leondtictors is forned on the substrate stirfaces within the PTOfOrmed grooves described above. To provide mear@s f<)r r@iatrix intraconnectioi a. plurality of tholes 40 (e.,a., FIGURE 5) is p.-ovided through the substrate, as by drillin.- the hardene!d substrate slice or by forming the hol-.s during molding. The holes are arran.-ed iu a pattern to connect grooves in rows on one surface to grooves i,@a o umns or. the other surface at predelermined intersection or crossover points. The patter-n of groove-connecting holes is sufficiently extensive to peri-nit flexibility in fitial circiii:t connections as deterniined by the particular circliit requiremen,@s of each planar module. Versatility of the basic module is provided in that t@'ie coreductor matrix and intraconnection thereof may bo, identical for each module with subseque..,it specific circuit designs accommodated simply by severing the matrix at desired poirts. After the aroove-connecting hol,@-s have been provided in the slibstrate siice, the matrix intraconnection pattern is defined in accordance with intercoinection of column grooves on one slarface of the substrate with row grooves on the other surface. Prefcrably, each through ho'e diameter is approximately equal to groove width to maintai,@i a coitinuous networlc of conductors lacirig ',he substrate. Addition of conductive material to grooves and holes of the substrate to form the condtictor matrix m. ay b.best accomplished by such methods as electroless plating or vapor deposition, although eleclroplating or brush plating processes may alternatively be employed. Each of these methods per se is well known in the art and falls within the generic classification of metaliz;n.- the substrate. Met@ils which are stiitable for use in the rneta'ilizing process to forni the intraconnected conductor matrix include gold, silver, copper, nickel, rhodium, tin, palladium cobalt, and chromium. In some cases a conductive undercoat may be desirable before de osifin, the final p conductive layer. However, the glass bonded mica substrate described above is readily coated by any of th-. a:bove-mentioned inetalizatioi and will generally not require undercoatilig to provide adhesion or adherence of the metallic conductors to the substrate. When the metalizing process has been completed th-, support substrate is surface ground on bol,h sides to remove all undesired conductive material from the Surface area betweer the para'llel conductors formed in the grooves so that no unwanted interconnections occur in the conductor matrix. The matrix, thus comprises a plurality of spaced lineal conduc' ors 45, 46 in a number of -roups of rows and columns conforming to the previous pattern of grooves and interconnected by throu.-hconductors 48 at various crossover points (FIGURE 6). As previoiisly me,itioiied, glass bonded mica substrates may be surface ground to optical flatness at miiiimum cost to provide smooth planar stirfaces. After grinding and/orpolishin,-, the stibstrate may be dipped ind glazed to protect th-. surfa,-e conductors. At this point, the substrate slice h-,is been sufficiertly prepared so that the microelectronic circuit chips m'ay be positioiied on and bonded to the substrate, The placement 6 of the cbips at stirface areas of the slice -,N;ill depbnd in large measure on the specific circuit design including the min-imizing of conductor len.aths for chips interconnections, abd may be readily accomplished by automated techniques. After positio-ti@'.ng of the chips 52 (FIGURES 5-7) on one or both surfaces of the substrate an integral 4bond is effectedtherebetween, preferably by thermo compression, to provide a multiplicity of circuit elenients inseparably associated within a continuous substrate body io and thus a completely integrated unit. The bonding temperatures employed will depend upon the par'ticular characteristics of the substrate and the circuit chips. Most of the suitable grades of glass borded mica substrates will withstand temperatures in excess of 700' F. applied on a 1,5 continuous basis (see above table) and higher temperatures if applied for short periods of tinie. Since the bondin,@ of the chips to the substrate rnay be accomplished in a relatively short length of time, temperatures i.Ti a range from 700' to 1000' F. have been found suitable for this 20 plirpose without harn to the substrate or to the component parts of the chips. After the chips have bee.,i bot-ided to the surface of the su,ostrate in integral relatio@i therewith the interconnection of the chip circuits via the rriatrix of conductors niay 25 be accomplished. Suitable forms of connection for this purpose are shown in FIGURES 5, 6 and 7. In FIGURE 5, the microelectronic circuit chips 5?. are positioned on and bonded to the substrate face-downwardly in "chipflip" arrangement, requiripg that appropriate holes be 3o drilled prior thereto through the substrate corresdording in position to the positions of the chip lands, tha-t is the conductive connection points on the face of the chips for the particular microelectropic circuit involved. In this case, since these holes have been previously metalized 35 to form conductors 56 dtiring the metalizin- step of the process, the thermo compressional bonding o'f the chip to the substrate providesa positive electrical and mechanical corince' ion between the conductor carrying holes and the chip lands, while s;niulta@icously providing an integral 40 connection between chip and sibstrate. The circuit arran,@ement of FIGURE 5 will also req,,jire additiopal parallel conducto@@s 53 departing from the standard rnatrix. To this extert, this arrangement is less desirab-le than those to be described. 45 The connection between microelectronic circuit chips 52 and 'the conductors 45, 46 within the matrix may b@more readily accomplished by use of co-@iductive leads which are applied to the chips lands and to the matrix conductors by ball thermo compression or welding tech50 niques. This arrang-,r@ient is shown in FIGURE 6. The leads 54 connecting the microelecl,ronic circuit to the conductors in the ma'trix have diameters on the order of 0.001 inch and hence special care is required to insure proper - rpcchanical and electrical connection. 55 The rnost desirable method of connecting the chip circuits to the conductive matrix is shown iTi FIGURE 7. In this method, the connectirg condticlors 62 are provided between the circuit lands and the matrix co-,iductors by vaciium deposition of conductive material with appro60 priate masking of other areas which are to rernain Lintouched. Conductors 62 may be deposited along the substrate surface with the chips 52 bonded as shown in FIGURE 6, but preferably the chips are bonded within special recesses or cavities 65 f-orming chip berths, each 65 cavity correspondin.- closely in d:@Dletisions to the dimens-tors of the chip itself. The depth of each cavity will be approximately equal to the dep,h of the matrix condi-ictor grooves and the cavities ther@'iselves preferably provided dliring the -inolding operation. After the chip has been 7o bonded to the substrate in its respective berth the leads or conductors 62 are deposited between the appropriate conductors in the matrix and the chip circuit lands. Extensions of copductors 62 across the surface of the substrate rnay lie in grooves provided by svitable maskin.- 75 and etching of t@%e substrate, with subsequent deposition
[4]7 of conductive material. Through conductors 68 are provided during prior drilling and metalizing steps. After bonding of the chip@ to the substrate and connection of the individual chip circuits to the conductor matrix have been completed, the subassembly which is provided up to this point is placed in a drill press or other appropriate apparatus for removal or severaiice of portions of the conductors to provide breaks in the n-atrix at predetermined points, e.g. 70 (FIGURE 6), for the purpose of providing the proper overall circuit tcrt--ninations. Since the formation of the final circuit with its ter@ninations is provided after the matrix has been applied to the substrate the value of the standardization of each rnodule is readily deseernible. Again, the removal of the conductor portions may be accomplished by the use Of tape controlled machine tool operations as previously described. At this point the complete circuit contailied within the module may be fully checked prior to completion of the overall assembly. Upon completion of the overall @ircuit testing the final module assembly is accomplished in the followin.- manner. A spacer plate 74 (FIGURES 2 and 3) of like material to that ol. substrate slice 14 and having a plurality of holes 77 correspondin.@ in position to the posit,'.On of microelectronic chips 52 on the stibstrate slice, is disposed over the substtate and chips, so that the chips (and associated leads if the arrangement of FIGURE 6 is utilized) lie within the botindaries of the mating holes, If the chips are borded to both surfaces of the slibstrate a pair of spacer plates will be employed. Otherwise, that is if only one surface of the substrate includes circuit chips, only oiie spacer plate need be provided. The substrate slice 52 and spacer plate 74 are suitably interposed between a pair of cover plates 80, 82 which are preferably of thin anodized aluminum alloy -,tnd which are coated with a thin insulative layer such as a ceramic glaze on at least those stirfaces wbich are to lie adjacent the substrate and spacer plate. Although other metallic plates may be employed it has been found that the anodized alumini-im alloy offers high resistance to damaging effects of radiation exposure, and are advantageous where such exposure is contemplated. To facilitate assembly of the four plates, that is cover plates 80, 82, the spacer plate 74 and substrate slice 14, each is preferibly provided with either a tongue or a groove seal such as illustrated by reference numerals 8,6, 87 (FIGURE 2). Such an arrangement permits lockin.- the plates in position to prevent false alignment of the several parts of the module. Those surfaces which are to -be placed adjac-nt one another will have provided thereon, respectively, a tongue seal and a groove seal, with the tongue of one plate fittiiig into the groove of the adjacent plate in locked assembly. When all four plates have been assembled into a single unit the outer edges of the plates are wetted, for example with indium solder, to hermetically seal the overall assembly. Indium is preferred as a solder seal because of its abii'ity to wet ceramic, glass and oxides as well as metals. The hermetically sealed planar module is thus protected against dust, dirt, moisture, fungus and so forth as might detrimentally effect performance and reliability of the circ,ait. The tongue and seal locking arrangement between plates of the assembly also provides a barrier a.-ainst the penetration of any sealant to the ipterior of the inodule which might cause shortina of the conductors and/or circuit connections. As a final measure of protection a thin metal band or frame 89, preferably of aluminum, is wrapped about the ends of the assembly to prevent interior circuit daina-,e due to external shock and vibration which may be transmitted by the module support panel. The frames or bands provide an elastic characteristic in the manner of spring washers, when several modules are stacked in a sin.-le container or panel, to absorb any impact loads or vibrations which may attend the operation of the device or craft within whic@ia the inodules are located. 3y3722310 An exemplary final modular assembly is shown in FIGURE 1, and in exploded view iii FIGURE 2 (without the sealing frame 89). Final modular packaaes have been constructed with dimensions on the order of 0.125 inch thick x 2.775 inch wide x 3.125 inch loiig, excluding external connector pin projections. In some instances the spacer plate or plites 74 may be unnecessary as where chip berths are provided and the step por'lion of the substrate is eliminated. In any c,,lse, the recessed chip It configuration of FIGURE 7 perp-iits the use o.'L spacer plates without apertures. While I have described certain specific embodiments and processes for practicing my invention, it will be understood that various changes and modiflcations in the 15 specific details of construction and particular process steps may be resorted to without effecting a departure from the true spirit aiid scope of the present invention. For example, the above described assembly consists of a single substrate having mat-rix conductors oriented relatively 20 transverse to those o-@i opposite surfaces and microelectronic circuits chips bonded to one or botii surfaces of the substrate in the gaps between the -roups of conductors of the matrix as the primary component of the pla-.iar module. However, the invention is intended to include multilayer 25 assemblies, that is a module containiiig several substrate layers with microelectronic circuit chips bonded on one or both sides of each surface layer, the substrates being separated by a spacer plate of molded construction as has been described, and to the various attendant modifications 30 of such multilayer packages. Moreover, conductors on opposed surfaces may cross at other than an angle of 90'. It is therefore desired that the present invention be limited only by the scope of the appended claims. I
