Error cancelling comparator based switch capacitor circuit and method thereof

An error canceling comparator based switch capacitor (CBSC) circuit cyclically works through multiple phases including a sampling phase and a transfer phase. During the sampling phase, an input voltage and also an error due to circuit non-idealities are sampled. During the transfer phase, the sampled input voltage is amplified by a fixed ratio and transferred to an output load, while the error is cancelled by reversing the polarity of connection for an internal capacitor within the CBSC circuit.

1. An error canceling comparator based switch capacitor (CBSC) circuit comprising:

a comparator, a charge pump circuit, and a plurality of capacitors;

wherein during a sampling phase the CBSC circuit samples both an input voltage and an error due to CBSC circuit non-idealities and during a transfer phase the CBSC amplifies the sampled input voltage and transfers a resultant voltage to a load while canceling the error by reversing a polarity of connection for at least one of said capacitors.

2. The CBSC circuit of claim 1, wherein the sampling phase comprises a preset sub-phase, a charge transfer sub-phase, and a hold sub-phase.

3. The CBSC circuit of claim 1, wherein the transfer phase comprises a preset sub-phase, a charge transfer sub-phase, and a hold sub-phase.

4. The CBSC circuit of claim 1, wherein the load comprises a capacitor.

5. The CBSC circuit of claim 1, wherein said capacitors comprise a sampling capacitor and an integrating capacitor.

6. The CBSC circuit of claim 5, wherein the sampling capacitor is coupled to the input voltage during the sampling phase.

7. The CBSC circuit of claim 6, wherein the integrating capacitor is coupled to the charge pump during the sampling phase, and also coupled to the charge pump during the transfer phase but in a reverse polarity.

8. The CBSC circuit of claim 1, wherein the CBSC circuit cyclically works through the sampling phase and the transfer phase.

9. The CBSC circuit of claim 8, wherein said capacitors comprise a sampling capacitor and an integrating capacitor.

10. The CBSC circuit of claim 9, wherein the sampling capacitor is coupled to the input voltage during the sampling phase.

11. The CBSC circuit of claim 10, wherein the integrating capacitor is coupled to the charge pump during the sampling phase, and also coupled to the charge pump during the transfer phase but in a reverse polarity.

12. The CBSC circuit of claim 9, wherein the integrating capacitor is coupled to the charge pump during the sampling phase, and also coupled to the charge pump during the transfer phase but in a reverse polarity.

13. A method of canceling error in a comparator based switch capacitor (CBSC) circuit comprising a comparator, a charge pump circuit, and a plurality of capacitors, the method comprising:

operating the CBSC circuit cyclically through a sampling phase and a transfer phase;

sampling an input voltage and an error due to CBSC circuit non-idealities during the sampling phase; and

amplifying and transferring the sampled input voltage to a load and canceling the error by reversing a polarity of connection for at least one of said capacitors.

14. The method of claim 13, wherein the load comprises a capacitor.

15. The method of claim 13, wherein the charge pump circuit comprises at least one of the following components: a current source and a current sink.

16. The method of claim 13, wherein the sampling phase comprises a preset sub-phase, a charge transfer sub-phase, and a hold sub-phase.

17. The method of claim 16, wherein the transfer phase comprises a preset sub-phase, a charge transfer sub-phase, and a hold sub-phase.

18. The method of claim 13, wherein said capacitors include a sampling capacitor and an integrating capacitor.

19. The method of claim 18, wherein the sampling capacitor is coupled to the input voltage during the sampling phase.

20. The method of claim 19, wherein the integrating capacitor is coupled to the charge pump during the sampling phase, and also coupled to the charge pump during the transfer phase but in a reverse polarity.

This application is related to the following copending application, owned by the assignee of this invention:

• • 1) Ser. No. 11/277,942, for “ERROR AVERAGING COMPARATOR BASED SWITCH CAPACITOR CIRCUIT AND METHOD THEREOF”
  • 2) Ser. No. 11/278,432, for “NOISE SHAPING COMPARATOR BASED SWITCH CAPACITOR CIRCUIT AND METHOD THEREOF”

1. Field of the Invention

The present invention relates to comparator based switch capacitor circuit, in particular to comparator based switch capacitor circuit that performs circuit error cancellation.

2. Description of Related Art

Comparator based switch capacitor (CBSC) circuit is an emerging technology that offers many advantages over conventional operational amplifier based switch capacitor circuit. Like a conventional switch capacitor circuit, a CBSC circuit also works in a two-phase manner. The two phases are “sampling” phase and “transfer” phase, controlled by two non-overlapping clocks, say φ₁and φ₂, respectively. In a typical two-phase CBSC circuit working at a sampling rate of f, the duration of each phase is slightly less than half of the sampling clock period T=1/f. During sampling phase (φ₁), an input voltage V_Iis sampled using a sampling capacitor C₁by connecting the “+” end of C₁to V_Iand the “−” end to a common mode voltage V_CM. During transfer phase (φ₂), the charge stored on the sampling capacitor C₁is transferred to an integrating capacitor C₂via a charge transfer circuit comprising a comparator 130 and a charge pump (CP) 140, which includes a current source I₁and a current sink I₂, as shown in FIG. 1. In FIG. 1, C_Lis a load capacitor for the CBSC circuit 100, V_DDis a supply voltage, V_SSis the lowest potential in the system. Note that V_CMis the common mode voltage that is usually close to the mean value of V_DDand V_SS. Also, C_Lis terminated to V_CMvia a sampling switch 150, which is controlled by a switch signal S. The purpose of the charge transfer circuit is to transfer the charge stored on C₁to C₂until the potentials on the two input ends of comparator 130 are equal, i.e. V_X=V_CM. The principle of the CBSC circuit 100 during transfer phase (φ₂) is briefly described as follows.

At the beginning of the charge transfer phase, a brief preset (P) must be performed to clear C_Land ensure the voltage V_Xis below V_CM. The preset is done by momentarily pulling the output node V_Oto V_SS, the lowest potential in the system. Next, a coarse charge transfer phase (E₁) begins. During coarse charge transfer phase, V_X<V_CMand CP 140 turns on the current source I₁to inject charge into the circuit comprising C_L, C₂, and C₁, resulting in a relatively fast voltage ramp on V_Xtoward V_CM. CP 140 continues to inject charge until comparator 130 detects V_X>V_CM. At the instant where comparator 130 detects V_X>V_CM, a fine charge transfer phase (E₂) commences by turning off the current source I₁and turning on the current sink I₂to drain charge from the circuit comprising C_L, C₁, and C₂. One deliberately chooses I₂to be lower than I₁, resulting in a relatively slow voltage ramp down on V_Xback toward V_CM. At the instant where the comparator 130 detects V_X<V_CMagain, the sampling switch 150 is opened and the charge stored on C_Lis sampled and frozen.

FIG. 2 depicts a typical timing diagram for the CBSC circuit 100 for the charge transfer phase. Initially the switch signal S is asserted. As a result, the sampling switch 150 is closed and the load C_Lis terminated to V_CM. In the mean while, V_Ostays at the sampled level from the previous cycle and V_Xis close to V_CM. The transfer phase φ₂, starting at time t₁and ending at time t₅, comprises four sub-phases: preset (P), coarse charge transfer (E₁), fine charge transfer (E₂), and hold (H). The CBSC circuit 100 first enters the P phase (at time t₁), where it pulls the output node V_Oto V_SSand causes V_Xto drop to V_XO, which is below V_CM. At time t₂, it enters the E₁phase, where comparator detects V_X<V_CMand CP 140 injects charge into the circuit comprising C_L, C₂, and C₁, resulting in relatively fast voltage ramp up on both V_Oand V_X. The E₂phase starts at time t₃, the instant where comparator 130 detects V_X>V_CM. Note that due to circuit delay, t₃slightly trails the exact time instant where V_Xrises past V_CM. During the E₂phase, CP 140 drains charge from the circuit comprising C_L, C₂, and C₁, resulting in a relatively slow voltage ramp down on both V_Oand V_X. Finally, the CBSC circuit 100 enters the H phase at time t₄, where comparator 130 detects V_X<V_CMagain. Again, due to circuit delay, t₄slightly trails the exact time instant where V_Xfalls past V_CM. During the H phase, S is de-asserted and thus the charge stored on C_Lis frozen, and also charge pump circuit CP 140 is disabled.

There are two problems associated with the prior art CBSC circuit 100. First, there is always an error on the final sampled value of V_Odue to the circuit delay. As clearly seen in FIG. 2, the actual sampled value is always slightly lower than the ideal sample value, which is the value at the exact time instant where V_Xfalls past V_CM. Second, the prior art CBSC circuit 100 is subject to error due to the offset in the comparator 130.

What is needed is a method to remove the errors due to circuit non-idealities, in particular circuit delay and comparator offset, for CBSC circuit.

In an embodiment, an error canceling comparator based switch capacitor (CBSC) circuit is disclosed; the circuit comprises a comparator, a charge pump circuit, and a plurality of capacitors; and the CBSC works cyclically through multiple phases including at least a sampling phase (φ₁) and a transfer phase (φ₂), wherein during the sampling phase (φ₁) the CBSC circuit samples both an input voltage and an error due to circuit non-idealities and during the transfer (φ₂) phase the CBSC amplifies the sampled input voltage by a fixed ratio and transfers a resultant voltage to a load capacitor while canceling the error by reversing a polarity of connection for an internal capacitor within the CBSC circuit.

In an embodiment, a method of canceling error in a comparator based switch capacitor (CBSC) is disclosed; the circuit comprises a comparator, a charge pump circuit, and a plurality of capacitors; and the method comprises: operating the CBSC circuit cyclically through multiple phases including at least a sampling phase (φ₁) and a transfer phase (φ₂), sampling an error due to circuit non-idealities during the sampling phase (φ₁), and canceling the error by reversing the polarity of connection for an internal capacitor within the CBSC circuit during the transfer phase (φ₂).

The present invention relates to error cancellation for comparator based switch capacitor (CBSC) circuit. While the specifications describe several example embodiments of the invention considered best modes of practicing the invention, it should be understood that the invention can be implemented in many ways and is not limited to the particular examples described below or to the particular manner in which any features of such examples are implemented.

The present invention is general and applicable to any sampled-data analog circuit. For example, the present invention can be applied to a pipeline ADC (analog-digital converter), and also to a delta-sigma ADC (analog-digital converter). A sampled-data analog circuit usually works in a multi-phase manner. By way of example but not limitation, a two-phase switch-capacitor circuit in accordance with the present invention is disclosed. Like the prior art described earlier, the two phases are sampling phase (φ₁) and transfer phase (φ₂). Without loss of generality, a pipeline ADC will be used as an example to illustrate the principle taught by the present invention.

In a preferred embodiment, the circuit configuration during sampling phase (φ₁) is depicted in FIG. 3. Here, the input voltage V_Iis sampled by C₁, just like the case in the prior art described earlier. At the same time, however, one also uses a CBSC circuit 100A that is exactly the same as the prior art CBSC 100 circuit shown in FIG. 1 except for the following changes: (1) C₁is replaced by C′₁, which has substantially the same capacitance as C₁, (2) C_Lis replaced by C′_L, which has substantially the same capacitance as C_L, (3) C₂is connected in a reverse polarity, and (4) an additional capacitor C′₂having substantially the same capacitance as C₂is connected in parallel with C′₁. CBSC 100A has substantially the same configuration as CBSC 100, and also works in a very similar manner.

An exemplary timing diagram for CBSC 100A is shown in FIG. 4, which is very similar to FIG. 2 except for (1) an additional signal R is used to clear up the respective charges stored on C′₁, C₂, and C′₂by connecting their both ends to V_CM, (2) clock φ₂is replaced by clock φ₁, (3) phases P, E₁, E₂, and H are replaced by P′, E′₁, E′₂, and H′, respectively, and (4) timing instants t₁to t₅are replaced by t′₁to t′₅, respectively. The signal R is momentarily asserted for a brief time and then de-asserted before time t′₁, where the sampling phase (φ₁) commences. Due to the signal R, both C′₁and C′₂have zero charge right before CBSC 100A enters the sampling phase (φ₁). The sampling phase (φ₁), starting at time t′₁and ending at time t′₅, comprises four sub-phases: preset (P′), coarse charge transfer (E′₁), fine charge transfer (E′₂), and hold (H′). The CBSC circuit 100A first enters the P′ phase (at time t′₁), where it pulls the output node V_Oto V_SSand causes V_Xto drop to V′_XO, which is below V_CM. At time t′₂, it enters the E′₂phase, where comparator detects V_X<V_CMand CP 140 injects charge into the circuit comprising C′_L, C₂, C′₁, and C′₂, resulting in relatively fast voltage ramp up on both V_Oand V_X. The E′₂phase starts at time t′₃, the instant where comparator 130 detects V_X>V_CM. Note that due to circuit delay, t′3 slightly trails the exact time instant where V_Xrises past V_CM. During the E′₂phase, CP 140 drains charge from the circuit comprising C′_L, C₂, C′₁, and C′₂, resulting in a relatively slow voltage ramp down on both V_Oand V_X. Finally, the CBSC circuit 100A enters the H′ phase at time t′₄, where comparator 130 detects V_X<V_CMagain. Again, due to circuit delay, t′₄slightly trails the exact time instant where V_Xfalls past V_CM. During the H′ phase, S is de-asserted and charge pump circuit CP 140 is disabled. Thus, the charges stored on C′₁, C′₂, C₂, and C′_Lare all frozen.

If CBSC 100A has zero comparator offset and zero circuit delay, then there will be zero charge on all for capacitors C′₁, C′₂, C₂, and C′_Lat the end of sampling phase (φ₁). However, due to nonzero comparator offset and circuit delay, there will be some charge stored for each of the four capacitors. Let the comparator offset be V_OS(i.e. comparator 130 favorably gives the “−” end an advantage in an amount of V_OSwhen performing comparison.) Let the current draining from C₂during E′₂be I. Also, let the circuit delay between the exact timing instant where V_Xfalls past V_CMand the actual timing instant where comparator 130 detects V_X<V_CMbe τ. Then, at the end of sampling phase (φ₁), the charges on C₁, C′₂, and C₂are:

Q1=C1⁡(V1-VCM)Q2′=-C2′⁢VOS+I⁢⁢τ⁢⁢C2′C1′+C2′
and
Q₂=−(C′₁+C′₂)V_OS+Iτ,
respectively.

In a preferred embodiment, the circuit configuration during transfer phase (φ₂) is depicted in FIG. 5. Here, one uses a CBSC circuit 100B that is substantially the same as the prior art CBSC 100 circuit shown in FIG. 1 except that the additional capacitor C′₂, which stores an error charge Q′₂at the end of the transfer phase (φ₁), is now connected in parallel with C₁. CBSC 100B has substantially the same configuration as CBSC 100, and also works in a similar manner.

An exemplary timing diagram for CBSC 100B is shown in FIG. 6, which is essentially the same as FIG. 2 except that the output voltage V_Ois exactly the same as the ideal sampled value at the end of the clock transfer. (Besides, unlike in FIG. 2 where comparator offset is not included, we have included in FIG. 6 an offset voltage V_OSin the V_Xwaveform.) The error due to comparator offset and circuit delay is cancelled due to the initial error charges Q′₂and Q₂stored on C′₂and C₂respectively. The exact cancellation is proved as follows.

In connecting C₁in parallel with C′₂, a charge sharing occurs to make the voltage across C₁identical with the voltage across C′₂. The initial value of V_Xright before CBSC 100B enters transfer phase (φ₂) is

VX(init)=VCM-Q1+Q2′C1+C2′

During P phase, V_Ois momentarily pulled low and so is V_X. During E₁phase, CP 140 injects charge so that V_Xrises toward V_CM+V_OS. Slightly after V_Xrises past V_CM+V_OS, E₂phase commences and CP 140 drains charge so that V_Xfalls toward V_CM+V_OS. Slightly after V_Xfalls past V_CM+V_OS, H phase commences and the charges stored on all four capacitors (C₁, C₂, C′₂, and C_L) are frozen. The final value of V_Xis then

VX(final)=VCM+VOS-I⁢⁢τC1+C2′

The total net charge transferred from C₁and C′₂to C₂during the entire transfer phase (φ₂) is then
Q₁=(C₁+C′₂)·(V_X^(final)−V_X^(init))

Therefore, at the end of transfer phase (φ₂), the charge stored on C₂is
Q₂^(final)=Q₂+Q_t=−(C′₁+C′₂)V_OS+Iτ+(C₁+C′₂)·(V_X^(final)−V_X^(init))

The final output voltage V_Ois then

VO(final)=VX(final)+Q2(final)C2

By manipulating above listed algebraic equations along with the conditions C′₁=C₁and C′₂=C₂, one obtains
V_O^(final)=V_CM+(V_I−V_CM)·C₁/C₂,

which is exactly the correct final output voltage for the case of zero comparator offset and zero circuit delay. The error due to comparator offset and circuit delay, therefore, has been completely cancelled.

For those of ordinary skill in the art, the principle disclosed by the present invention can be practiced in various alternative forms, including the following:

• • 1. In an embodiment, one may pull the output voltage V_Oto V_DD, the highest potential of the system, during the preset (P or P′) phase, thus forcing the condition V_X>V_CMbefore entering the coarse transfer phase (E₁or E′₁). In that scenario, I₁needs to be changed to a current sink while I₂needs to be changed to a current source.
  • 2. In an embodiment, one may totally eliminate the fine transfer phases E′₂and E₂, as the error due to circuit delay will be completely eliminated and therefore there is no need to use a fine transfer phase to reduce the error caused by circuit delay. In this case, the I₂current is eliminated, and the overall operation speed of the switch capacitor circuit improves.
  • 3. In an embodiment, one may use a differential circuit instead of a single-ended circuit. FIG. 7 depicts an exemplary circuit that is a differential counterpart to the single-ended circuit depicted in FIG. 5 for the sampling phase (φ₁). Note that although the fine transfer phase E′₂is eliminated in CP 140A of FIG. 7, for those of ordinary skill in the art it is straightforward to include the fine transfer phase by adding a current source I₂₊ and a current sink I₂₋that are both controlled by E′₂. Also, for those of ordinary skill in the art, it is straightforward to use a similar way to construct a differential counterpart to the single-ended circuit depicted in FIG. 6 for the transfer phase (φ₂).
  • 4. In an embodiment, during transfer phase (φ₂), the “+” end of capacitor C₁and/or the “+” end of capacitor C′₂in FIG. 5 may be connected to a voltage different from V_CM. For example, for a pipeline ADC application, the “+” end of either capacitor may be connected to one of many other predefined voltages depending on the range of the voltage V_I. The principle taught by the present invention, however, applies equally well to that scenario.
  • 5. In a further embodiment, the capacitor C′₂is implemented using a plurality of capacitors, which are connected in parallel during the sampling phase (φ₁), but during the transfer phase (φ₂) their “+” ends may be connected to different voltages, each chosen from either among many predefined voltages or connected to an internal node within the system. The principle taught by the present invention, however, applies equally well to that scenario.
  • 6. In a further embodiment, one may choose to clear up the charges on C₂, C′₁, and C′₂(by asserting the R signal) following the end of the transfer phase (φ₂), instead of preceding the beginning of the sampling phase (φ₁).

Also, there are many switches (besides switch 150) that are needed but not displayed in any of the figures. They are controlled by a plurality of clock signals to define the circuit configuration (i.e. the connections among circuit elements) for both sampling phase (φ₁) and transfer phase (φ₂). They are not shown in the figures because they are implied and deemed obvious to those of ordinary skill in the art.

Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.