[1]This application claims the benefit of provisional Application Serial No. 60/164,555, filed on Nov. 10, 1999, the contents of which is hereby incorporated by reference.
BACKGROUND OF THE INVENTION
[2]1. Field of the Invention
[3]This invention generally relates to gate-controlled switches, and more particularly to a gate turn-off thyristor which achieves enhanced performance through an improvement in turn-off current commutation.
[4]2. Description of the Related Art
[5]Gate turn-off (GTO) thyrisitor switches are the foundation of the high-power electronics industry. Structurally, GTO thyristors are four-layered, three-terminal silicon semiconductor devices which resemble a traditional thyristor in terms of performance but has the additional attribute that anode current can be turned off by control of its gate. Traditionally, a GTO's turn-off performance is limited by the slow gate current rising rate, and the turn-off is conducted with a turn-off gain (defined as Ia/Igat turn-off point) in the range of 3 to 5. Major drawbacks of the GTO include: 1) large gate control power due to the fact that the gate current has to be supplied for a long time; 2) slow switching speed due to long storage time; and 3) poor turn-off Safe Operation Area (SOA) due to non-uniform current distribution during turn-off. Because of the poor SOA problem, a GTO turn-off requires a dV/dt snubber, typically in the form of an R-C-D network. The RCD snubber is not only bulky, but also very lossy because each time the GTO turns on it will have to dissipate the energy stored in the snubber capacitor. The slow switching speed and high control power limits GTO's application in high frequency Pulse Width Modulation (PWM) converters.
[6]In recent years, the turn-off performance of GTO thyristors has been significantly improved by turning it off at the unity-gain condition (Ig=Iaat turn-off). By taking this approach, also known as hard-driven approach, the turn-off storage time has been shortened from typically several tens of microseconds to about one microsecond. The maximum turn-off current hence the SOA of these GTO thyristors has been significantly increased and the bulky and costly dv/dt snubber can be removed. High-power, hard-driven GTO thyristors can operate at frequencies of one kilohertz or above in a practical application system. See Motto et al. “The Emitter Turn-Off Thyristor (ETO) Based High Voltage, High Frequency Converter System,” 1999 Center for Power Electronics Systems Annual Power Electronics Seminar, pages 340-345.
[7]The condition known as unity gain turn-off corresponds to a situation where the cathode current is completely commutated to its gate before the end of the storage stage, or before the anode voltage increases. The essence of this is to break the PNPN latch-up mechanism, changing the GTO into an open-base PNP transistor mode during the turn-off transient. Typically, the GTO has a storage time of 1 microsecond under the unity gain turn-off condition. Therefore, the current commutating rate has to be very high (˜anode current/1 μsec) for high-current GTOs.
[8]Three major methods (devices) have been reported for operating GTOs in the unity turn-off gain condition. The first method was applied to an emitter turn-off (ETO) thyristor which made use of two switches to realize the high turn-off current commutation. During turn-off, its emitter switch QEis turned off while the gate switch QGis turned on. A voltage as high as the breakdown voltage of QEcan be applied on the gate loop stray inductor LG, realizing fast current commutation. See Li et al., “Introducing the Emitter Turn-Off Thyristor (ETO),” IEEE Industry Applications Society 33rd Annual Meeting, Oct. 12-15, 1998, pages 860-864.
[9]The second method was applied to a MOS turn-off (MTO) thyristor. This device was implemented using only a gate switch QGDuring turn-off, the gate switch is turned on, bypassing the current through the GTO gate-cathode diode and realizing unity gain turn-off. See Piccone et al., “The MTO Thyristor—A new High Power Bipolar MOS Thyristor,” IEEE Industry Applications Society 31st Annual Meeting, Oct. 6-10, 1996, pages 1472-1473.
[10]The third method was applied to an integrated gate commutated thyristor (IGCT) . This IGCT uses one voltage source and one gate switch. By dramatically decreasing the gate loop stray inductance, a high current commutation rate is achieved in the IGCT.
[11]Each of the aforementioned devices has inherent limitations which degrade performance. The emitter switch of the ETO thyristor needs to conduct the main current, so it is implemented by paralleling many MOSFETs. The turn-off voltage for the current commutation in the MTO thyristor is less than the forward voltage drop of the GTO gate-cathode diode, so the current commutation rate is low.
[12]Insofar as the IGCT is concerned, it is indisputable that the turn-off current commutation diG/dt is crucial to the performance of this type of device. As has been reported in the previously referenced Yamamoto article, even under the unity gain turn-off condition, higher commutation di/dt ensures a more uniform turn-off transient process over the entire GTO thyristor wafer. This, in turn, increases the turn-off capability of the device. Nevertheless, conventional IGCT devices remain limited by the turn-off loop stray inductance and the maximum turn-off voltage, the latter of which is typically about 20 V.
[13]More specifically, in conventional IGCT devices a further increase of the turn-off current commutation diG/dt is difficult because of its gate loop stray inductance LGand the maximum available voltage source VOFFthat can be used. For example, the gate loop stray inductance of a 4-inch IGCT has been reduced to 3 nH, which is considered to be very low and is even harder to decrease. The maximum gate turn-off voltage that can be applied to the IGCT has to be less than the breakdown voltage of the GTO's gate-cathode diode. Because this breakdown voltage is typically about 20 V, a maximum of about 6 kA/μsec commutating di/dt is achievable. See Yamamoto et al., “GCT (Gate Commutated Turn-Off) Thyristor and Gate Drive Circuit,” PESC 1998, pages 1711-1715. The use of such a low maximum turn-off voltage has adversely affected the performance of the IGCT.
[14]In view of the foregoing discussion, it is clear that a need exists for an improved gate turn-off thyristor which has fewer limitations than its conventional counterparts, and more specifically one in the form of an integrated gate commutated thyristor which operates based on a higher maximum turn-off voltage and thus with enhanced performance than conventionally possible in IGCT devices.
SUMMARY OF THE INVENTION
[15]It is a first object of the present invention to provide a gate turn-off thyristor switch which has improved performance compared with conventional gate turn-off thyristor switches.
[16]It is a second object of the present invention to achieve the first object by increasing the turn-off current commutation diG/dt to values above that achievable by conventional IGCT, ETO, and MTO devices.
[17]The foregoing and other objects of the invention are achieved by providing a gate turn-off thyristor circuit which, in accordance with one embodiment, includes a gate turn-off thyristor connected to an anode, a diode connected in series with the gate turn-off thyristor and a cathode, a turn-off voltage source connected to the diode, and a gate loop stray inductance element connected between the turn-off voltage source and the gate turn-off thyristor. In this arrangement, the diode is a discrete diode. Its breakdown voltage may therefore be selected to be a very high value. This, in turn, allows for use of a high turn-off voltage Voffto achieve a very high turn-off current commutation diG/dt which enables the GTO thyristor circuit of the present invention to achieve enhanced performance while maintaining a relatively simple circuit design. Also, the thyristor circuit of the present invention operates with equivalent performance as an integrated gate commutated thyristor in the aspect of unity turn-off gain, fast turn-off transient, and snubberless turn-off capability.
[18]A second embodiment of the thyristor circuit of the present invention resembles the first embodiment except that a plurality of diodes are connected in parallel between the gate turn-off thyristor and a cathode terminal.
[19]A third embodiment of the thyristor circuit of the present invention resembles the first embodiment except that a single diode wafer is packaged with the GTO inside the GTO's press-pak.
[20]High current/power semiconductor devices are crucial to modern industry, and gate turn-off thyristors are the only practical candidate. The thyristor of the present invention significantly improves the performance of high-current GTOs, leading to improved power electronics and industry application. Furthermore, the invention is economically feasible to implement in terms of cost and ease of design.
BRIEF DESCRIPTION OF THE DRAWINGS
[21]FIGS. 1(a), (b), and (c) show equivalent circuits for an integrated gate commutated thyristor, an emitter turn-off thyristor, and an MTO thyristor.
[22]FIG. 2 is a diagram showing a thyristor circuit in accordance with one embodiment of the present invention;
[23]FIG. 3 is a graph showing waveforms corresponding to an anode current, anode voltage, cathode voltage, and gate current for the embodiment of the thyristor of FIG. 2;
[24]FIG. 4 is a diagram of a simulation equivalent circuit for the turn-off transient of the thyristor of the present invention;
[25]FIG. 5 is a graph showing simulation results obtained for a simulation of the thyristor of the present invention, wherein an unexpected current injection occurs during the turn-off transient;
[26]FIG. 6 is a graph showing simulation results wherein the current injection disappears by selecting the turn-off voltage VOFFto be higher than the breakdown voltage DE;
[27]FIG. 7(a) is a photograph showing a prototype thyristor constructed in accordance with a second embodiment of the present invention, and FIG. 7(b) is a schematic diagram of the circuit shown in FIG. 7(a).
[28]FIG. 8 is a graph showing snubberless turn-off waveforms obtained in accordance with the prototype thyristor of the present invention;
[29]FIG. 9 is a graph showing voltages obtained for the thyristor of the present invention during the turn-off transient;
[30]FIGS. 10(a)-(d) are circuit diagrams and additional graphs of internal voltage waveforms obtained during the turn-off transient;
[31]FIG. 11 is a diagram of how the thyristor of the present invention may be packaged; and
[32]FIG. 12 shows how a third embodiment of the thyristor circuit of the present invention may be packaged.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
[33]The present invention is an improved gate turn-off thyristor circuit which has a higher turn-off current commutation diG/dt than conventional gate-controlled thyristors. This higher commutation is achieved by connecting at least one diode in series with a gate turn-off thyristor. The breakdown voltage of the diode is selected so that the breakdown voltage of the gate to cathode is increased above the conventional breakdown level, which is typically 20 volts. Because the new thyristor of the invention operates at a higher breakdown voltage, it is able to outperform conventional gate-controlled thyristors while simultaneously maintaining a very simple and economical design.
Principle of Operation
[34]Referring to FIG. 2, a gate turn-off thyristor circuit in accordance with a first embodiment of the present invention includes a gate turn-off thyristor GTO constructed from alternating layers of P- and N-type semiconductor material. Unlike the IGCT device of FIG. 1(a), a diode DEis connected in series with the gate turn-off thyristor GTO, an anode terminal A is connected to the GTO and a cathode terminal C is connected to the diode. Diode DEis part of a loop circuit which includes a voltage source VOFF, a turn-off switch QG, and an inductor LGconnected to one of the P-layers of the GTO. The breakdown voltage of the GTO gate-cathode diode is VGC, the breakdown voltage of diode DEis BVE, the turn-off voltage source is VOFF, and the gate loop stray inductance is LG.
[35]FIG. 3 is a graph of waveforms corresponding to the expected anode current IA, anode voltage VA, cathode current IC, and gate current IGof the circuit shown in FIG. 2. During a time period between t0and t1, which corresponds to a turn-off transient, the turn-off switch QGis turned on. As a result, the turn-off voltage source VOFFis applied on the gate loop stray inductance LGwhile DEand DGCare conducting. The turn-off current commutating rate may be expressed as:
[37]where the basic limitation of VOFFis VOFF<VGC+VDE.
[38]In this arrangement, since DEis a discrete diode its breakdown voltage can be selected to be very high. As a result, a very high value of the turn-off current commutation diG/dt can be achieved by using a higher value of VOFF. This, in turn, allows the thyristor circuit of the present invention to achieve a maximum turn-off voltage well above the 20 volt level of conventional GTO thyristors, thereby achieving enhanced performance in terms of gate drive power reduction, fast turn-off transient, and snubberless turn-off capability.
[39]Returning to FIG. 3, once the forward current in DEand DGCreaches zero, the GTO enters into the so-called unity turn-off condition. However, the current in inductor LGwill keep increasing after t, until both diodes DGCand DEfinish their reverse recovery and block voltage. To limit over-current commutation, a fast reverse recovery diode is preferably used for DE. By the end of this reverse recovery process, at t2, the current through the two diodes comes back and stays at zero before the end of the storage time. These diodes also serve to block the gate power supply voltage VOFF.
[40]At the end of the storage stage, t3, the anode voltage begins to increase. At time t4, the anode voltage reaches the DC link value and the anode current begins to decrease. The maximum gate current decay rate, which is determined by the gate loop parameters VOFF, VGC, VDE, and LG, may be slower than that of the anode current fall. Reverse breakdown will occur for both diodes DEand DCGuntil time t5when the gate current reaches the current tail level.
[41]Based on the above analysis, it is clear that the gate turn-off thyristor circuit of the present invention realizes a higher turn-off current commutation rate compared with conventional GTO devices by making use of the diode DE. Moreover, the unity turn-off gain is realized very quickly and can be maintained until the end of the turn-off transient process.
[42]The thyristor circuit of the present invention can also be implemented in a very simple manner. By making use of a single diode die of a size equal to the GTO, the thyristor of the present invention may be made simply by stacking the two dies together and packaged inside a single press-pak (in accordance with a third embodiment of the invention). The component count is therefore low compared with ETO and MTO thyristor devices. Furthermore, because the press-pack diode has proven to be reliable over the long term, the reliability of the gate turn-off thyristor circuit of the invention will also be high. The forward voltage drop of this invention, however, will increase.
Design
[43]The gate turn-off thyristor circuit of the present invention may be designed so that the minimum turn-off voltage is defined as Voff=LG*(diG/dt). Since the storage time of a GTO under the unity gain condition is typically less than 1 μsec, the dIg/dt has to be high enough so that the gate current is equal to or higher than the anode current within 1 μsec. For example, to turn-off 6 kA, the dIg/dt has to be higher than 6 kA/μs. With certain margins, a dIg/dt of 8 kA/μs is needed. If the loop inductance is 30 nH, this would require a VOFFof VOFF=0.02 μH * 8 kA/μs=160 V. This high voltage can be used in the present invention but not the conventional GTO or IGCT because it is beyond the limits of a GTO's gate-to-cathode breakdown voltage, BVGC.
[44]The design of the breakdown voltage BVEof diode DEis very important to the snubberless turn-off capability of the thyristor of the invention. First, the condition BVE+BVGC>VOFFhas to be met so that the power supply VOFFdoes not constantly break down the gate-cathode junction of the newly invented device. However, selecting a too high BVEis not desirable.
[45]Simulation results show that if BVEis higher than the turn-off voltage VOFF, an effective forward gate current injection, which attempts to turn the GTO on while its voltage is rising, is presented after the unity-gain has already been established. This kind of effective current injection is detrimental to the snubberless switched GTO, because of the interaction which takes place within the gate current commutation loop.
[46]FIG. 4 shows an equivalent circuit used for Pspice simulation when a 60 volt DEand a 55 volt turn-off power supply VOFFare used. Serious current injection into the GTO emitter diode DGCis found both before and after the anode current fall. FIG. 5 shows simulation results of the circuit shown in FIG. 4.
[47]Referring to FIG. 5, when all the cathode current is commutated to the GTO gate (i.e., unity-gain is established), DEand DGCenter into reverse recovery mode. In their recovery stage, the turn-off voltage source VOFFwill build an opposite current into the GTO cathode and extra energy in LG. Because diode DEis designed with a shorter reverse recovery time than DGCto avoid excess reverse current being built in DGC, diode DEwill recover earlier and block VOFF. Since VOFFis less than BVE, the extra energy in LGwill now be discharged by transferring to the junction capacitance CDEof DEand breaking it down. The gate current begins to decrease at a rate of:
[49]After a while, the GTO gate-cathode diode will also be recovered and will breakdown as well due to LGenergy. The maximum gate current decreasing rate will be:
[50]dIG/dt=(BVE+BVG−VOFF)/LG
[51]This dIG/dt is much higher than the previous one and brings the gate current to the anode current level rapidly, as shown in FIG. 5. After the extra energy in LGis discharged (at this time IG=IAagain), the extra energy stored in DGCand CDEwill discharge in the opposite direction (forward direction), and could complete discharge CDGCif the extra voltage on DGCwhen it breaks down is more than half of BVGC(one can view this as an oscillation process between LG-CDGC-CDE). If this happens, an effective forward injecting current exists in the GTO via DGC(i.e., the emitter junction of the GTO). A similar transient process with a forward injection will also occur during the anode current fall (see FIG. 5). This is also caused by energy stored in LGand the oscillation between LG-CGC-CDE. These injections will cause device turn-off failure and the device will be destroyed.
[52]By designing BVElower than VOFF, so that BVGC/2+BVE<VOFF, the effective current injection problem can be solved because the reverse biased GC junction will never be fully discharged during any LG-CGC-CDEoscillation..
[53]FIG. 6 shows simulation results when the turnoff voltage VOFFis increased to 70 volts. The current in DGCdoes not flow forward once it is commutated. The voltage across this junction VDGCremains negative also. This ensures that the GTO will always operate in the open-base PNP mode with no thyristor action. Large voltage can therefore be established across the GTO without failure. This will therefore ensure the large turn-off SOA achieved by the present invention. Moreover, the device of the present invention with no forward injection can therefore conduct turn-off without any dV/dt snubber. This is also called snubberless turn-off capability.
Experimental Demonstration
[54]An experimental gate turn-off thyristor circuit in accordance with a second embodiment of the present invention was developed, as shown in FIG. 7(a), based on the aforementioned principles. The diode DEin this circuit was implemented by paralleling two or more discrete diodes, as schematically shown in FIG. 7(b). The GTO was a 53 mm 1.0 kA/4.5 kV device manufactured by Westcode Semiconductor. The breakdown voltage of DEwas 55 volts, and the turn-off voltage VOFFwas 60 volts. Once the GTO was turned off under the unity turn-off gain condition, the uniformity of the current distribution was guaranteed. Theoretical and experimental results showed that the turn-off capability of the GTO was limited only by the dynamic breakdown, which was about 200-300 kW/cm2. This ensured the snubberless turn-off capability of the thyristor circuit of the invention.
[55]FIG. 8 shows the snubber less turn-off waveform of the thyristor at 0.8 kA, 1.5 kV DC link voltage. As these results show, the GTO's gate and cathode voltage waveform can be used to estimate the turn-off current commutation rate diG/dt and the gate loop stray inductance LG.
[56]FIG. 9 shows voltage values obtained by the thyristor circuit of the present invention during the turn-off transient. The experimental circuit discussed above demonstrated that a much higher turn-off voltage VOFFcan be used for current commutation than that of a IGCT. In conjunction with a reduction in the gate loop stray inductance, the current commutation rate of the thyristor circuit of the invention can be much higher than 6 kA/μsec. IGCT requires 3 nH construction to obtain 6 kA/us current commutation rate. Since reducing inductance is not easy and economical, the present invention allows the same commutation rate to be achieved with must higher stray inductance. For example, if LG=15 nH, the present invention can still obtain 6 kA/us by using VOFF=90 V.
[57]FIGS. 10(a)-(d) are circuit diagrams and additional graphs of internal waveforms obtained during the turn-off transient. FIGS. 10(a) and (b) define the voltage Vtoffand Vdas measured by an oscilloscope. Since most of the gate loop inductance LGis inside the GTO package, Vtoffincludes the voltage on most of LG. At time t=t12, diode DEhas recovered and the gate current commutation rate changes to that given by dIG/dt=(BVDE−VOFF)/LG.
[58]At time t=t2, diode DGC(GTO's emitter junction) has recovered and broken down. This brings down the gate current to the anode current level.
[59]A bump in Vdfrom t2to t4is due to the discharge of CDE(hence CDGCas well) in the forward direction (this is the cause of the possible forward injection). However, in this case, the discharge of CDEand CGC(not shown in the diagram) is not enough to forward bias DGC.
[60]From t4to t5, GTO emitter junction is in breaking down again to allow energy in LGto be discharged. The DC voltage difference between VtOFFand Vdis the reverse voltage applied to the GTO's emitter junction.
[61]FIG. 10(c) shows the definition of Vgk(Vgk=VtOFF−Vd) as measured by an oscilloscope that is shown in FIG. 10(d). Before time t12, the high voltage Vgkrepresents voltage applied to LGfor rapid commutation to achieve unity turn-off gain. This voltage drops quickly as soon as the diode DErecovers at time t12. After time t12, a constant voltage close to 20 V is applied to the GTO's GC junction (plus part of LG) which ensures reverse biasing of the GTO.
[62]Six-inch GTOs have been commercialized for several years, having more than twice the die area of 4-inch devices. However, a 6-inch device is not expected to switch twice as much as the 4-inch IGCT. There are two reasons for this. The first is that the gate driver cannot supply a high enough current commutation rate (12 kA/μsec) to ensure the unit turn-off gain. The second relates to the uniformity of the turn-off transient process. An even higher current commutation rate is needed to avoid current crowding in 6-inch IGCTs. The principles embodied in the thyristor of the present invention may be used to achieve this goal. For a six-inch GTO, the gate loop inductance is expected to be between 15 nH and 20 nH if a design similar to FIG. 7(a) is used. To achieve a 12 kA/us commutation rate, it may be preferably to use VOFF=180 V and a diode with BVE=170 V.
[63]FIG. 11 shows the thyristor of the present invention using a packaged GTO in series with a single packaged diode.
[64]FIG. 12 shows how a third embodiment of the thyristor circuit of the present invention may be packaged. In this embodiment, a GTO die/wafer and a diode die/wafer are stacked and combined in a press-pak housing, with the anode and cathode terminals above and below the package.
[65]Other modifications and variations to the invention will be apparent to those skilled in the art from the foregoing disclosure. Thus, while only certain embodiments of the invention have been specifically described herein, it will be apparent that numerous modifications may be made thereto without departing from the spirit and scope of the invention.
