[1]United States Patent Office 31335,489 3,335,489 INTERCONNECTING CIRCUITS WITH A GALLIUM AND INDIUM EUTECTIC William E. Grant, Placentia, Calif., assignor to North American Aviation, Inc. Filed Sept. 24,1962, Ser. No. 225,804 1 Claim. (Cl. 29-628) This invention pertains to a method of making interconnections in multilayer pripted wiring boards having two or more printed wiring patterns interconnected through holes in electrically insulating material. Since the advent of semi-conductor devices, a continued effort has been made to miniaturize circuits and, since the development of solid-state circuit devices comprising semi-conductor wafers on which functional electronic circuits are etched, an effort has been made to miniaturize coniplete systems through miniaturized printed wiring boards for interconnecting solid-state circuit devices. The latter may be referred to as microminiaturization to distinguish from the earlier effort of miniaturizing circuits throtigh the use of rniniature tubes, transistors, and the like, connected by so-called printed circuit boards to form functional circuits that are interconnected through wiring in back of a panel or rack on which the boards are mounted to form a system. In a nlicrominiaturized system en-iployin.- solid-state circuits, or similar devices, printed wiring boards are employed to interconnect solid-state circuit devices that may be mounted on the boards which may in turn be interconnected through back panel wiring if necessary to form a larger system. Maximum compactness of printed wiring boards is desired for either miniaturization or microminiaturization. To achieve compactness, both sides of a board supporting printed wiring pattems are often utilized, particu ar where cross-over connections are required, with intercon.nections through an insulating layer as desired. For microminiaturization it is often desirable to fabricate printed wiring boards having three or more superimposed wiring patterns separated by substrates comprising sheets of electrically insulating material throli.-h which the desired electrical interconnections are made. The provision of cornpact miniature interconnections throug@h the insulating material of a double-sided printed wiring board has been a problem. A commonly used tech_ nique has been to mechanically place a lead pin, eyelet, rivet or staple through the board and, in or@er to assure electrical continuity, to solder both ends thereof to conductors of respective printed wiring patterns. Another technique has been to plate through connecting holes. The mechanical technique is reliable but not totally satisfactory because of the limit imposed on ibe minimum distance between centers of such connectors and on the minimum distance between superimposed multilayer boards. The plating technique overcomes the limitations of the mechanical technique and is reliable, but does present some problems in fabricatingmultilayer printed wiring boards. For example, a plated interconnection does not itself provide a firm base for thermo-compression bondin- of components or solid-state circuit devices to the outside layers. The object of this invention is to provide a method for making improved interconnections in multilayer printed wiring boards. Patented Aug. 15, 1967 2 According to the invention, a hole or perforation drilled or etched through a printed wiring board at a point where an interconnection is desired is filled with a metal alloy while in a liquid phase (referred to hereinafter as a liquid solution) at room temperature, such as an admixture of mercury, gallium or indium c)r a eutectic of at least one of them with one or more -other metals such as copper, silver or gold or other electrically conductive metals in such proportions that all interalloying elements form a 10 transitional liquid phase with no change in temperature for a period sufficient to work the mixture into the interconnecting holes, whereupon it will solidify and assume a fusion temperature several bundred degrees hi.-her than the original solution temperature. This is in contrast with 15 solder mixtures which consistently melt and solidify at their inherently specific temperatures. The present conductive alloy, whirh remains liquid for a relatively short time at room temperature, once solidified will remain a solid solution over a range of temperatures from -50' to 20 500' C. Thus, when first mixed at room temperature, between 24' to 30' C., the conductive alloy will be liquid for a short time and then will solidify at this temperature. The melting point of the solid alloy will exceed 500' C. before it again liquifies. Any mixture of metals may be 25 employed if they form a liquid solution at a low temperature for a sufficiently long period to allow it to be worked into the hole before solidifying, but alloys formed using mercury, gallium or indium, particularly alloys of gallium and indium, are preferred because they remain 30 solid at much higher temperatures than the low temperature at which solidification takes place. Although particular examples of suitable alloys are described, it should be understood that many other alloys may be selected by reference to phase diagrams such as those presented by 35 Max Hansen in Constitution of Binary Alloys, Metallurgy and Metallurgical Engincerin-, Series, McGraw-Hill Bc)ok Co. (1958). For the purpose of describing the present invention, an alloy is defined as one or more low 40 melting point metals, or a cutectic of a low melting point metal, rnixed with one or more other metals to form a liquid solution that, due to the low melting point metal or eutectic in the mixture, can be worked for an appreciable interval of time before solidifying at room temper45 ature or at some relatively low processing temperature. The manner and process of making and using the present invention is described witti reference tG the drawings in which: 50 FIG. I illustrates a blank board having connecting holes throuah its insulating material; FIG. 2 illustrates the blank board of FIG. I after the connecting holes have been fflled with an alloy in accordance with the present invention and a desired wiring 55 pattern has been etched on the copper sheets; and FIG. 3 illustrates the manner in which the present invention may be adapted to a method of fabricating multilayered printed wiring boards. In order to utilize the present invention to best advan60 tage, the interconnecting holes are made in a blank board before the wiring patterns are etched, as illustrated by the drilled doiible-clad board of FIG. 1. A supporting base or substrate 10 made of electricaliy insulating material, 65 such as an epoxy resin impre.-nated glass cloth, is laminated with two thin sheets <)f copper 11 and 12. Holes 13
[2]32335;489 3 and 14 are etched through the @eopper sheet 11 at points where interconnections are desired using a ferric chloride solution, or some suitable etching solution such as ammonium persulphate, which will not etch the resin impregnated glass cloth of the substrate 10. After the holes 13 and 14 have been etched through the copper sheet 11, holes are etched through the substrate 10, such as a hole 15, using the etched copper sheet 11 as a mask, such as with a solution of hydrofluoric and sulfuric acids which will not d,.ssolve the copper sheets 11 and 12. The etchin.- time for the substrate 10 is dependent upon its thickness, but can be reduced and controlled by proper agitation of the solution. The hole 15 is etched through the substrate 10 to the inner surface 16 of the :copper sheet 12. The etch g process is allowed to continue until a sufficient surface -,area 16 of the copper sheet 12 is exposed for the purpose of making an electrical connection thereto. It should be noted that as the etching process of the insulating substrate 10 proceeds, the inner surface or underside of the copper sheet 11 is exposed due to the etching of the substrate 10 at a rather uniform rate in all directions from the center of the hole 14. The resulting undercut 17 around the hole 14 could be removed by a second etching process, but that is not essential for the practice of the present invention even though it may be desirable to enlarge the hole 14 in order to facilitate better filling with an alloy in accor . dance with the present invention. The alloy to be worked into the connecting holes is spread, rolled, or oiherwise applied, to the copper sheet 11 while in the liquid phase until the holes, such as the concentric holes 14 and 15, are filled from the upper surface 16 of the lower sheet of copper 12 to the upper surface of the upper copper sheet 11. The-alloy is preferably -compressed or maintained under vacuum or a combination of these, while filling the holes to obtain bet@ter compaction and greater alloy density within the holes. In addition, the alloy fill may be allowed to solidify at an elevated temperature and pressure, such as at 350' F. under a pressure of 150 p.s.i., during which time the alloy fill may exude any excess liquid metal for proper mixing of the liquid metal with the solid metal to form a solution which will pass from a liquid phase to a solid phase at that temperature. After the alloy fill in the connecting holes has been allowed t-o com-pletely solidif@, the desired wiring patterns may be etched into the copper sheets 11 and 12 with a solution of ferric chloride. FIG. 2 illustrates the board of FIG. I having the connecting holes 13 and 14 filled and the desired wiring pattems etched into the copper sheets 11 and 12. The alloy fill 18 in the hole 14 is shown in ,cross section in order to -point out that due to the undercut in the insulation sheet IO.around the hole 14, pockets of entrapped air, such as pockets 19 and 20, may be formed. Those pockets do not materially detract from the electrical continuity desired between the conductiv-. sheets 11 and 12 throu,-h the alloy fill 18 in the hole 14, but to obtain more complete filling, the board may be placed iri a vacuum chamber before t-he alloy fill 18 is allowed to solidify and the desired wirin- pattern etched, thereby drawing out entrapped air and allowing the alloy to more completely fill the hole. The following t@@ble of some alloys which may be employed to practice the invention is to be considered as illusttative of several embodiments of the invention and not as an exhaustive list of all the embodiments possible. Other alloys may be more suitable for certain applications or methods of fabrication. Accordingly, although a suitable alloy may be selected from the table for most printed wiring board applicat-ions, other alloys may be selected from the art, particularly binary alloys, as by reference to the phase diagrams in Constitution of Binary Alloys refeited to hereinbefore. 4 PE, RCE, NT OF CONSTITUENT METALS Ga Au Cu Eg Ag Sn In 5 1 ----------- 18 82 -------- -------- ------ -- -------- -------- 2 ----------- 34 66 -------- -------- ------ -- -------- -------- 3 ----------- 35 65 -------- -------- ------ -- -------- ------ - 4 ----------- 30 64 -------- -------- ------ -- -------- -------- 5 ----------- 41 59 -------- -------- ------ -- -------- -------- 6--- - -- 34 33 33 -------- -------- -------- -------- 7 ----------- 30 49 -------- -------- 21 -------- -------- 10 8 ----------- 32 -------- 44 -------- -------- 24 -------- 9 - ---- 32 ---- 50 -------- -------- 18 -------- 16 ---------- 36 -------- 60 -------- -------- 4 -------- 11 ---------- 45 -------- 50 -------- -------- 5 -------- 12 - ------ 68 -------- 25 -------- -------- 7 -------- 13 ---------- 34 -------- 66 -------- -------- -------- -------- 14 ---------- ------- -------- -------- 70 30 -------- -------- 15 ---------- -------- ---- 30 70 -------- -------- ---- 15 16 ---------- -------- -------- -------- - ------ 30 -------- 17 ---------- 26. 6 65 --- -------- -------- 8. 4 18 ---------- 32.2 65 2.8 -------- 19 ---------- 32.2 65 -------- -------- 2.8 -------- 20 ---------- -------- -------- -------- -------- 40 -------- 20 The first five exa-mples of t-he foregoing table iepresent the range of useful percentages of the liquid metal gallium alloyed with gold. If the gallium is reduced -to less than 18%, the mixture is too dry and incomplete mixing to form an alloy of all of the gold results. If 25 the gallium is increased to more than 41%, the mixture is too wet and a solid solution @may not result. Accordingly the more limited inter-niediate range of 34 to 36% gallium is preferred for more -uniform results. Liquid solutions in that range pass into the solid phase at room 30 temperature in about ei-ht hours. After the solidification process has been completed, t-he solid solution will remain sufficiently hard at teniperatures exceeding 500' C. By the ter@m sufficiently hard it is meant that the alloy will have a predetermined resistance tO plastic deformation 35 UsLially by indentation. A similar range of working percentages of gallium @and any other metal, such as silver or copper, may be developed by referrin-.to the phase dia.-rams of the parr 0 ticular alloy. Similarly, alloys of otbe low melting point 40 metals, such as mercury and indium, may be considered and a preferred ran,-e for uniform results defined by reference to phase dia@rams. The characteristics of an alloy @may be altered by the addition of one or more me@tals. For instance, in the 45 Example 6 of the foregoin.- table, copper has been substituted for half of the gold in the second exa-mple. The resultin@ alloy requires the same period of time to sol@dify (about eight hours) but will remain sufficiently hard at hi.-her temperatures (as high as 650' C.) than the second 5o exam@ple. By the substitution of silver in the Example 7, an alloy results -with a shorter solidifying period and a lower cliseful range of temperatures. More specifically, the Example 7 will solidify in about two hours and remains sufficiently hard to a temperature of about 425' C. 55 The next five Examples 8 to 12 include gallium, copper and tin in different proportions. The Examples 8 and 9 require a long period to solidify (about 24 hours), but remain sufflciently hard at temperatures as high as 650' a,d 700' C., respectively. The next two Examples 10 60 and I 1 contain less tin and completely solidify in a shorter period of time (about 4 to 6 hours) while the Example 12 requires a longer period of time (about 24 to 48 hours) due to the larger proportion of gallium. In general, a lon.cer solidifying period provides a longer 65 period to work the alloy into the holes since, as a rule, the working period is about 5 ito 15% of the solidifying period. Accordingly, a Ion,-er solidifying period is preferred as long as the resulting alloy is sufficiently hard. 70 For instance, the Example 12 provides a long working period, but the resulting alloy was found to be a soft metal that may not be satisfactory in some applications of the invention. The next Example 13 is an alloy of gallium and copper 75 Which is similar to the Example 2 but remains sufficiently
[3]3133-5;489 hard at -higher temperatures up to about 900' C. Com parin.- it to the Examples 8 to 12 coiitaining tin, it may be seen that the presence of tin provides a longer solidifyin.- time but produces a hard alloy only if the proportion of gallium is held low. Accordin.-ly, a eutectic of gallium and tin with 64 to -66% copper is preferable, particularly since the addition of tin reduces the useful range of the alloy. The followin.a Examples 14 and 15 are alloys of mercury. The Example 14 is an alloy of mercury and silver sometimes employed in diffeie-nt proportions as a dental amalgam. It solidifies in about three hours and melts at 276' C. The Example 15, an alloy of mercury and copper, is similar and also satisfactory for the practice of the invention since it forms a solid solution at room temperature (22.2' C.) and melts at 96' C. The next Exa-mple 16, an alloy of indium and silver, is similar to the Example 14, except that it has a higher formation temperature since p@ure indium melts at 156.4' C. and does not melt below 400' C. Other binary or ternary alloys of indium may be advanta.- eously employed, particularly when the printed wiring board is apt to be used in environn-ients at hi.-her temperatures. For instance, a powdered mixture of equal parts of gold and indium may be used to fill the @holes after which the printed wiring board may be @placed in an oven until the mixture reaches 156.4' C., the melting temperature of indium, at which temperature a liquid solut;on of indium and gold is formed. T@hat solution forms a solid solution at that temperature and remains sufficiently hard at higher temperatures up to about 500' C. Like all of the alloys under consideration, the indium-gold alloy is stable in the solid solution at all temperatures below room temperature. The next Example 17 is the preferred alloy comprisin,@ a eutectic of gallium and indium mixed with 65% gold. The percentage of gold may be varied by as much as 5% with results as satisfactory as with Examples 2, 3 and 4. A eutectic is a solution of two or more metals having its components in such proportions that the meltin.- point of the solution is -t-h@ lowest possible with those components. As such, the proportions for any eutectic can be ascertained by the standard techniques of stoichiolnetry, but for the practice of the present invention it is not necessary that the proportions ascertained be followed in mixing the eutectic to the same degree of accuracy as the degree of accuracy to which @the proportions are determined since the percentage of the eutectic itself in the mixture of the alloy is not critical. The advantage of usin.- a eutectic is that it has a lower melting temperature than its component metals. For instance, the eutectic of gallitim and indium has a melting poiiit of 16' C. whereas gallium alone has a melting point of 29.75' C. Exainple 18 is another alloy formed from a eutectic, namely a eutectic of galliurn and tin. The eutectic is mixed with gold iii the sarne proportion,as in the Examples 3 and 17. The eutectic has a melting point of 20' C. so that it is easier to form an alloy with other n-ietals such as gold in the Example 18 or copper in the Example 19. If even higher ternperatures of forinatioi can be tolerated than that of Example 16 which forms an alloy at temperatures higher than the melting temperature 156.4' C. of indium, other alloys may be employed such as binary alloys of tin. The last Example 20 is an alloy of that type consisting of 40% tin and 60% gold. At 232' C. the tin melts and alloys with the gold to provide a liquid or plastic soltition for a period of time before the solid solution is formed. The alloy thus formed remains hard to a temperature of about 500' C. Since, as noted hereinbefore, alloys of gallium, @indium or mercury tend to expand as they harden, if such ati alloy is used, the evacuated pockets in the perforat-ons are readily fuled by the expanding alloy. Further expansion after the evacuated pockets have been filled will not materially affect the board because the alloys of gallium 6 or indium packed into the holes tend to compress rather than build up pressure due to expansion, and what pressure is produced is greatly relieved thr-ough the hole 14. After the alloy has been allowed to solidify, the excess alloy on the surface of the copper sheet 11 may be removed by some suitable -inethod, as by abrading. Thereafter, the entire surface of the board may be copper plated, if desired, in order to provide a protective copper film over the alloy filling of the holes 13 and 14 before 10 the desired wirin.@ patterns are etched, but that is not necessary as the alloy will withstand wear and further processin.- of the board during the fabrication of additional layers. For greater assurance of proper electrical continuity 15 between the circuits etched in the copper sheets 11 and 12, the etched holes 13 and 14 in the copper sheet 11 may be enlarged after theconnecting holes have been etched tbrou-h the insulatin.- material of the substrate 10, as noted hereinbefore, in order to facilitate complete 20 fillina of the holes. For even greater assurance ofcontinuity, the holes may be copper plated before filling, as by first electroless platin.- and then elector platin,-. The resultin,@ copper pjating throu.-h the hole may itsel,f provide the desired continuity between the sheets 11 and 12 25 as in the prior art, but reliance is placed on the alloy fill in accordance with the. present invention with the advanta,@e that a firm interconnection is provided for bondiDg component or solid-state circuit devices. It should be noted that the interconnecting holes may 30 be made in some other manner and in some other shape, as by drilling or punching instead of etching, but the -etchin.- method is preferred because a large number of holes may be etche-d throu,-h a board simultaneously and, since the etching processes rnay be controlled, the holes may 35 be placed as close together as necessary, limited only by the process employed for coatin.- the exposed surfaces of the copper sheets 11 and 12 with a filni which will resist the copper etching solution and by any undercut produced by the process of etching the insulating material 10. 40 A mechanical drill or punch, on the other hand, has the disadvantage of being capable of punching only one hole at a time on centers only as close as the mechanical drill fixtures and control means will allow. It shoiild be further noted that although the method 45 for makin,@ t@he connecting holes has been described as a one-sided process of etchin.- from one side to the inner surface of the copper sheet on the other side of the substrate 10, a two-sided process may be employed by simply etching holes through both of the copper sheets 50 11 and 12 simultaneously and etching the insulating material of the substrate 10 from @both sides. If a two-sided etchin.- proces is used, a backine sheet of some suitable material, preferably one to which the alloy fill will not adhere, should be provided while working the alloy into 55 the holes in order to insured complete filling. The expansion of the alloy as it solidifies assures proper electrical contact with th-. copper sheets 11 and 12. The manner in which the electrical connectors provided in accordance wit-h the -present invention may be utilized 60 advantageously to fabricate multilayered circuit boards is illustrated in FIG. 3 by showing an exploded view of three circuit layers etched o-@i substrates 21, 22 and 23. The first circuit layer is fabricated on the substrate 21 in a manner similar to that described with reference to FIGS. 65 1 and 2, with the exception that the bottom sheet of copper (not shown) - laminated to the substrate 21 is not etched until all of the inner wiring layers have been fabricated, in order to protect or mask the insulating material 70 of t@he substrate 21 during substrate etching processes. Interconnections A and B which pass throuah the substrate 21 are fabricated in accordance with the method of the present invention before the next printed wiring layer on @the substrate 22 is laminated to the first printed wirin.- 75 layer on the substrate 21.
[4]7 Tbe next printed wiring layer may be fabricated by laminating to the substrate 21 a sheet of insulating material for the substrate 22 with a copper sheet lami a to it on its upper surface and etchin.- holes C' an through the substrate 22 to pads C and D on the substrate 21. The holes C' and D' are then filled with an alloy in the manner described with reference to FIG. 2 before etching the wiring pattern shown on t-he substrate 22, which includes a pad E to be connected to a third printed wiring layer etched on the substrate 23. The third layer may be fabricated in a similar manner, etching the holes D" and E' after the substrate 23 has been laminated to the substrate 22, and fillin- the holes D" and E' with alloy to provide interc.6nnections with the filled hole D' and the conductive pad E on the substrate 22, before etching the third wiring pattern. If the twrd wiring pattern is the last layer to be fa:bricated, the desired wiring pattem on the bottom side of the substrate 21 may be etched at the same time. A more detailed description of this overall metliod of fabricatin.- multilayer boards is described in a copending application fil,-d concurrently herewith by Joseph M. Shaheen and Henry F. Jones, and assigned to the assignee of this invention. A multilayered board fabricated in the manner just described utilizing the electrical interconnections of the present invention will ocrupy only that space which the ,superimposed layers <)f the laminated boards require and desired interconnections are readily provided in a reliable manner through either one layer, such as the interconnecti<)n E' to the conductive pad E tbrough the substrate 23, or a number of layers, such as the interconnections D' and D" to the conductive pad D on the substrate 21. It is emphasized, however, that the present inventi-on is not in the method of producing the interconnecting holes nor in the overall method of fabricatin.- multilayered printed wiring boards, but in the method of producing an ele@r,trical interconnection through an existin-. hole with a metal all<)y and the interconnections produced thereby. While particular examples of the invention have been described, it will be understood that the invention is not limited thereto since many modifications may be made in the examples with respect to the materials, proportions, temperature, pressure and time in keepin- with the con32335@489 are not to be limited to the partictilar examples, but to the true spirit and scope of the invention. W at is
