[1]United StatesPatent Office 3,198@95.9 3,193,959 LOGIC SYSTEM EMPLOYING TUNi'iiw@L DIODE TI-IAT IS BOTH D.C. AND CLOCK-PULSED BIAS-PD Br@;a.n ElHoff Sear, Creland, Pa., ass--gnor to Sperry'.Rand Corporation, r-iew Yoyk, N.Y., a corporation of Delaware Filed Feb. 14, 1962, Ser. No. 173,251 12 Claims. (Cl. 307-88.5) This invention relates to a system of circuits for providinlogic flnctions. In particular, the system includes circuits which provide the logical AND operation and the lo,@ical OR operation and includes a circuit for invertin-- the fu-@iction perfornrd by the AND or the OR circi@its. Each of the circuits in the system utilizes tunnel diodes as the active or switching. components thereof. In the construction of many large electronic systems, as for example lar,-e scale computin.- machines, the utilizatio-ri of standard lo.-ic notation is oftentimes either required or desir--d. Moreover, it is the usual pract;ce, for practical and econonical reasons, to provide standardized circuits for pen'ormin- the normal logic functions. Cor.sequently, AND circuits, OR circuits apd inversion circuits and the trlth tabl.-s therel'Or are known in the art. Various eir@-uits have been designed to perform -these functions. Howe,,,er, the invention of the tunnel diode has provided another circuit cop-iponent whic-h has advantageous characteristics which are oft,-n desirable to utilize in constructing circuits for lo.-ic systerfis. Thus, this circuit system utilizes tu-iinel diodes as the a,@tiv-- components th-.rein whereby the extremely high speed operation oil the tu@in,-l diode operation may be utilized such that the lo.-ic syster@i nay be capable of performing operations faster. The proposed system utiliz--s AND circuits, OR circuits and inversion circuits. However, it is to be understood that each of these circuits may be utilized sepaTately and indep.-ndently. Thiis, the innention shows circuits utilizing -a tunnel diode as th-- active switching element thereof which switches in accordance with the input information supplied by a diode clust.-r. The switchin- of the tunnel diode is effected by the application of a clock si,-nal which eff-.ctively sampl,-s the input diode clustet and provides switchin.- (or not) of the tunnel diode on a current sharin.- basis. The output is produced at one elec,trode of th-- tupnel diode and may be supplied to another diode cluster which may r--present the input diode cluster for a further similar circuit. It may be seen that the invention includes an AND eircu;t and an OR circuit as well ,as an AND-OR complementary logic system. The type of eirciiit operation is depend.-nt upon the sp-.cific arrangement of the tunnel diode in the circuit. I-Ti some instances, it may be desirable to effe-@t thaini,ersion of one of the -preced;n.- stages tfiereby effectin.a substantially the function of a NOR circuit. The ;nversion stage again utilizes a tunnel d:@ode which is switched from on,- state to the other by a clock signal in acco@i-dance with current sharing principles and the input information appli-.d to the input diode cluster associat--d ther,-with. A.-ain, th-- specific circuit operation isdei)endent iii)on the sp--cific arran.-ement of the I-annel diode. This circuit arran.-ement provides larg--r fan-in primarily because the reverse leakage of the coupling diodes can be made small. Moreover, fan-out may be made larg--r than in analo.- threshold circuits. Furthermore, -hi.-her speed are possible since the driving source or clock source Nvhich switch-.s the tunnel diodes can be a low impedance source. These advantages are advanta.- es which are desirable in the fabrication of any large scal.- system utilizin.- logical circuits. @From the foregoing, it may be seen that one object of this invention is to provide a high speed logical system. Patented Aug. 3, 1965 2 Anoth.-r object of this invention is to provide a high speed logical system Nvhich has wide tolerances on the compon--nts and the driving sources. Another object of this invention is to provide a high speed logical system with lar,,e fan-in, fan-out properties. 5 Aiother object of this invention is to provide a logic system in which th-- number of components per logical element is minimized. Another object of this inventi6n is to provide a hi,,,h speed logical system having co-mplementary logic compo10 nents' These and other objects and advanta.-cs of this invention will become more readily apparent s&osequeri-t to a study of the following description which is to be read in conjunctio-@l with the attached drawings in wh; : 15 FIGURE I repre.@ents the V-I characteristics for a typical cbupling diod-- of the circuit; FIGURE 2 represents the V-1 characteristics of a typical tunnel diode utilized in the circuit; FIGURE 3 shows one embodiment of a system utilizing 20 complem@@ntai-y AND-OR logic with inversion of the AND logic components; FIGURE 4 is a timing diagra-,n which is applicable to the embodiment shown in FIGURE 3; @FIGURE 5 shows a furth--r embodiment of the system 25 utilizing A.ND-OR complementary logic Nvith inversion of the OR logic elements; and FIGURF, 6 shows,a timing diagram which i@ applicable to the system embodiments shown in FIGUR7E 5. Peferring now to FIGURE 1, there is shown a typical 30 V-I characteris@lic for a diode. This characteristic comprises the hi.-h iinpedance, low,conductance region 102 and the high conductance, low impedance r@-gion 104. The definition of the regions is well known and is not necessary to be established. These regions are conventionally 35 denoted as being separated arbitrarily by t-he breakpoint 100 which designates the forward voltage Vp. In different diodes, the relative values of the different regions vary considerably. LTi the circuits shown subsequently, the coupling diodes may be, for exarnple, Fairchild type 40 -FD1150diodes. Thesediodesaresilicondiodesandmay have a potential of approximately 400 millivglts as thebreakpoint potential. That is, VI, equals approximately 400 millivolts. Thus, wh,-n the potential difference across the diodes is less than 400 millivolts the diode acts as a 45 very large impedance (ideally the diode acts as an open circuit). On the contraty, when th@- potential across the diod-- exceeds the brealcpoint potential, the diod-- acts substantially as a short circuit (in the ideal cas--). In practice, 50 the impedance varies between approximately 50 ohms and 1 megohm in the different staaes. Referring now to FIGURE 2, there is shown a typical V-1 characteristic for a tunnel diode. In the circuits of the system shonvn subseque-iitly, the tunnel diode may 55 be for exa.-nple a type lN651 manufactured by Texas Instruments. This tunnel diode is a gallium arsenide tunnel diode which has higher voltage and current handlirg capacities and is used in the inversion or negation circuits described subsequently. The tunnel diodes uti60 lized in the AND or OR circuits may be G.E. type lN2941 diodes which are germanium and have lower values at corresponding operating points. As usual, the V-1 characteristic for a tunnel diode may be broken into three regions which are well known. The regions are the peak region 206, the negative resistance region 65 203 and the forward region 210. According to the deiinition, -the regions are found to be defined by the peak voltage point 200, the valley voltage point 202 and the forward voltage point 204. Typical values for the potential for the diodes desi,-nated are: peak voltage V,@ 70 eqi-7als 50(Ge), 100(GAs); valley voltage, V, equals 350(Ge), 450(GAs); afid forward voltage, Vf equals
[2]500(Ge), ll'OO(GAs); where the values are given in milli,iolts. Likewise, the value for the peak current lp is approximately 5(Ge), IO(GAS) where the values are ,-iven in milliamperes. In a typical application, the bias current IB is approximately 0.7 lp. Referring now to FIGURE 3, there is shown a circuit system utilizing the basic circuit concept and providing AND, OR and inverting logic functions. The AND circuits are des;,-nated as P stages; the OR circuits are designated as N stag,-s; and the inverted AND gate is desi,-nated as a P' sta,-e. This desi,-nation of the sta,-es is somewhat arbitrary but is also mnemonic iiasmuch as the P circuit comprises a tunnel diode biased positively Nvith respect to ground apd the N circuit comprises a tunnel diode biased negatively with respect to ground. The P' stage comprises a tunnel diode which is biased to be floalin.- relative to grotind but is related to the P circuit in operation. As shown in FIGURE 3, the system comprises several lo.-ic circu;ts of which the first P stage has for the input couT)Iin@ means thereof, the diodes 302. These diod.-s which may be silicon diodes for example have the cathodes thereof connected to receive input signals. As shown, there may be Q input diodes each of which has the anode thereof connected to the anode of tunnel diode 300. Tunnel diode 300 may be, for example, a germanium diode of the IN2941 type manafactured by G.E. The anode of 'tunnel diode 300 is further connected via resistor 304 to voltage source 306. The source 306 provides a potential on the order of about +10 volts with respect to ground. The source 306 and resistor 304 are utilized to provide a s,.ibstantiauy constant current source for the tu-,inel diode. This constant current source biases the tunnel diode 300 to the point 212 of FIGURE 2. The cathode of the tunnel diode 300 is returned to ground whereby the biasing oj' the tunnel diode anode above ground is effected. Also connected to the anode of tunnel d,',ode 300, is the cathode of diode 310 wh,.ch has the anode thereof connected to clock source 3fiS. The clock source provides periodic si.-nals which have a potential of about +1.0 volt and which endure for approximately 2- nanoseconds. These positive goin.a clock signals provid-. an input sampling operation. Reset diode 313 has the anode thereof connected to the anode of tunnel diode 300 and the cathode thereof conrected to reset clocl, source 315. Source 315 provides signals Nvhich are substantially th@. inverse of the signals supplied by source 308, but supplied prior thereto. Reset clock 315 caases tunpel diode 300 to be switcbed to the low voltage operating state. The output from the PI stage is provided at the anode of the tunnel diode 300. In accordance with the provisiors of this circuit, the cii-cuit can drive R outputs. These R outputs are represented by the diodes 312 each of which has the anode thereof connected to the anode of tunnel diode 300. It is to b-, understood of course, that the "output" diodes 312 (which are also silicon type diodes), may in actuality represent the input diodes to ftirther circuits. That is, the individual circuits shown do not necessarily incorporate both Q input diodes and R output d;odes. Thus, as shown in .1@IGURE 3, one of the output diodes 31'. is connected as one of the Q input diodes Nvbi-,h drive the succeeding N, stage. TI-@e Q input diodes 312, 312a are connected to the cathode of tunnel diode 322 Nvhich has the anode thereof co-@inected to groiind whereby the cathode of the tunnel diode is effecti,iely biased to a regative potential. Also co,-inected to the cathode of tunnel diode 322 is resistor 320 and the anode of diode 314. The cathode of d@iode 314 is connected to the clock source 316 @vhich provides -round poten'ial referenced negative going pulses similar in ma@nitude to those supplied by source 303 except out ol phase therewith. The resistor 320 counles the volta,-e source 318 to ttinnel diode 322 thereby effect-ng a stibdiode to the low voltag.- state. Reset diode 323 has ,he cathode thereof connccted to the cathode of tunnel diode 322 and the anode thercof conn@-ctcd to reset clock solirce 325. The si.-nals supplied by this source are positive goin.a with respect to ground and serve a function s;milar to the signals of source 315. The R otitput signals derived from the N, stage are provided at the cathode of the t@annel diode 322. A-.ain the outputs are represented by diodes 324 cach of which has 10 the cathode thereof connected to the cathode of tunnel diode 322 and the anode thereof connected to a succeedir.-L, stage. That is, the so-called output diodes 324 are, in effect, identical with the input diodes 324a of the succeedin.- sta.-e. 15 The P' sta,,@e as in the case ol' the preceding stages is driven by R input diodcs 324 and 32'@a. Th-- anodes o-f tli-- input diodes are connected to th-, catbode of the tuiriel diode 330. The tunnel diode in the P' stage a -allium arsenide tunnel diode for example a lN651 20 diode ma.-@ufactured by Texas Instruments. It will be scen that the tunnel diode 330 is not grounded at either electrode thereof but rather is con-@iected (at the anode) to a pos;tive potential soi-irce 332 via resistor 356 a@id (at the cathed.-) to a negative potential source 323 via 25 resistor 326. The poten'lial soi-irces -'-32 and 728 each provide a potential, the magnitude of wmch is about 10 volts. Inasmuch. as these potertial sources are substantially ident,'.cal, the tunr-iel diode effectively is fioatin.ab-,iit -round. Thus, when the tunnel diode is biased 30 to tiie low voltage co-@idition shown ir. FIGURF- 2, t@ic anode aid cat'iiode e,- ,hibit potentials of approx,mately +50 and -50 millivolts, respectively. The cat@ode of tunnel d-ode 330 is coupled to a further pot-,ntial source 342 via @iode 340. The source 342 provides a potential 35 of about -200 niillivolts. This circuit is effective to clarr@p the tannel diode when outp-,,ts a.-c bein.- derived therefrom. A clock source 334, w'@iich provides signals similar to those previously described is connected to tli.- anode of tunnel diode 330 via diode 336. ReseL 40 diode 339 is connected between reset source 341 and the anode of tunnel diode 330 in order that the tunnel diode may be controllably switched to the low voltage op--ratipg state. Reset clock source 341 provides negative going signals siniiiar to those supplied by source 45 315. The R outputs provided by the P' stage are derived at the diodes 333 each of which has the anode thereof connected to the anode of tunnel diode 330. A.@ain, the R output diodes are alsorepresentative of the Q input diodes 338a which drive the succeeding 50 sta.-C. The N2 sta.-C which is driven by si.-nals applied to the innut d;@odos 33Sa comprises a tunnel diode 3E;2 Nvhich has the anode thereof -rounded and the cathode thereof connected to the cathodes ol. the input diodes 338, 33oa. 55 The cathode of tunnel diode 352 is connected to sources R6 and 348 by diode 344 and resistor 350, resl)ectively. Source 346 is a clock source similar to the previously described clock sources and proviaes sj'gnals which are ne.-ative goiilg wilh respect to -round pot,-ntial. The 60 soarce 3LA3 provides a potential of about -10 volts such that in cor.-.bination with resistor 350 a substantially constant current is supplied to tlinnel diode 352 whereby the ttinnel diode is biased in the low voltage state. Reset diode 353 hqs the cathode thereof connected to the cathode 65 of ttinnel diode 352 E,@nd t'.ie anode thereof connected to reset clock source 355. Source 355 provides positive goin.@ signals which roset tunnel diode 353 to the low voltage operating state. In stage 1,T2 the outt)uts are derived Lrom the cathode of ',unnel diod@, 352 an-d are presented 70 v,@'a outp,-,t diodes 352. As noted supra, th,- output diodes of any stage may, in 'Lact, represent the -inptit diodes of tle succeeding staec, and riay in fact be omitted. At leas@ one of d-odes 2,54 may, in fact, be considered as being iclcr@tical to a@ lcpst one of diodes -,@@D2 such th.,it a recircustantia'lly co.,istant current source wmch biases the tunnel 75 latin.@ typ-- of circuit may be provided.
[3]The operation of the circuit shown in I-IIGURE 3 is more 'Lully underst,-ndable vihen described in conjunction with the timing diagram shown in .1:71GURE 4. l@t is to be underslood, of course, that the clocking arrangement shown is illustrati-,ie only ani is not meani to be limitatiN,.- of the invent:@on. The set si.-nal is the sig-.ial which is utilized to saw-ple the input to the circuit -@vhere as the reset signal is utilized to switch the tinnel diode back -to the low volta.ae state, if necessary. In the case of the P or P' circuits, a set signal is a positive -Oing signal and th-@ reset signal is a ne.-ative going signal with respect to ground potential. In th-- case of the N stages, the set signal ;s a negative -oin.- signal and the resi-t signal is a positive goi@-i- sigqal. It will be se@-n that thougn the system as described is a four phase clocking arran.aement, the clockin- may actualiy be comprised of two clock sources which are 90' out of phase, each of @vhich is fed to a circuit directly and also to ahother circuit through an inverter thereby providin.- a four phase arran-ement. Also as shown in FIGU'@@E 4, the clock si.1nal may be construed as be;ng a substantially pulse type si.-nal as for example shown by the solid line, or in the alternative, it may be considered to besubstantially lev@-1 type si.-nals (substant:lally lo--ger than the pulse si,-nal previously described) and shown by a dashed line in FIGURE 4. 1-he specific duralion of the clock signals is ,lot meant to be a portion of the invention per se. As a matler of explanat;on, it should be understood that the input signa,s supplied to sta,@e PI (si,-nal Input PI) is an arbitrary si.-nal aD:,,Ii,-d to illustrate the operatioii of the overall systcm. @--'or illustrative purposes only, it is assumed that the Input Pl- si.- nal is supplied 'by a pr-,ced-in.@ N stage or the li@'@e st@ch that the signal will switch between -50 and -500 millivolts. It should be understood that the o-@,tput signal providcd by any of the N stages varies betw-@en -50 and -500 millivolts. Contrariwise, th-. output signal Lrom the P sta.-es varies betweeil +50 and +500 millivolts. Also, the P' stage in7,,erts the input si,-nal suppl;.ed thereto as will beco@ne n-iore readily kdparent subsequently' Moreover, it wiH be assumed init:.ally, that each of the sta.-cs shown have been respt; that is, the tlnnel diodes in each of the circuits shov,,n ar@- op--ratiii.- ;- I the low voltage coi-dit@'@on. The stage PI set clock signal supplied by clock source 308 is applied at time period tO. As suggested supra the clock A si,-nal may be a pulce at time period tO or it may be a level signal which c,@ists until time period tl. D-Liring the applicat-lon of the set clock signal, the input signal applied to the cat@hode of diode 302 and thereby to stage Pl, is deilned as being a high level signal or a si,-nal of approximately -50 irillivolts. This input signal is supplied to the sta,--- PI via one of the Q input diodes 3@12. For purposes of illustration, it is assumed that each of t-.@e Q input diodes has applied thereto a similar signal whereby each of the input diodes 302 are rev@-rs.- biased. These diodes are reverse biased inasmuch as they are dio,des which according to the characteristics thereof require a potenlial drop thereacross on the order of about 400 nillivolts in ord,-r to exceed the breakpoint of the diod-- charac,lerteristic. Viit!i a smaller potential dr 011) thereacross, the diodes may be considered effectively as lar.-e irlpedances (ideally the diodes are open circuits). lr-ip.smuch as the tunnel diode 309 was initially biased in th,- low voltage condition, the potential at the anode of the diode is approximately +50 mirivolts. Tberefore, the voltage drop between the anode and the cathode of the diode 302 would be on the order of approximately 100 ni ;Ilivolts. This potential diferelice is represented by the operati-,i.- point IC-6 on the diode characteristic shown in FIGURE 1. Clearly, the ir@put diode acts at a very hi.-h iriipedance. Co-ilsequently, the application of tl'",.- s-,t clor-k si,-iial by source 30'0 via diode 3110 raises the potential at the anode of tunnel diode 300 to a level which is greater than the valley voltage. Thus, the tunnel diode will be switched froni the low voltage state 31198,959 to the bigh voltage state. When the tunnel diode 300 is in the high voltage state, the anode thereof exhibits a potential of about +500 milliv6lts. Thus, it may be seen that source 306 and resistor 304 effectively comprise a steady state constant current source of about 0.7 lp (where lp is the peak current) which biases the tunnel diode to the low voltage state but that th.- application of a set signal by clock source 308 via diode 310 to the tunnel diode 300 is effective to switch the tunnel diode to 10 the hi,-a voltage state. The input signal to stage PI is purely arbitrary with the illustration herein and this signal is shown to terniinate between time periods tl and t2. On the contrary, t-he output signal from stage PI remains at the high level inasmuch as the tinnel diode 15 was switched to the high voltage state and remains thereat until reset. At tirne period t2, the resel clock soarce 3jl5 presents a reset signal to the circuit. That is, source 315 provides a negative-going signal via diode 313. Once a@-ain, the input and;ou,put diodes are back20 biased (i.e., -the anodes thereof are driven negative with respect to ground). The reset signal at diode 313 may be cons,idered to draw current from the tunnel diode 300 or to reduce the potential at the anode thereof to such a degree that the operating point of the tunnel diode is 25 effectively moved below the valley point, whence the tunnel diode will switch from the high voltage state to the low voltage state. The potential at the ano-de Gf the tunnel diode, therefore, will switch from +500 to +50 millivolts which potential is applied to the aiiodes of @qo th-- output diodes 312. The output signals will r--main at the low level until a furt@her set clock signal is applied simtiltancously with the application of a high level signal to the input of the circuit so as to produce a current through the tunnel diode which is sufficient to switch said 35 tunnel diode. At time p--riod t4 the next set clock s;gnal is apinlied to sta,@e PI. In this instarce, a Dotent-@'al c@.: apDrox-.'Malcly -500 mill:@volts is applied to the cathode of at ieast or.,e of the input diodes 302. Inasritich as t,ic anode is 4o at appro,,,imately +50 n-iillivolts and the cathode is at approximately -500 m-illivolts, it may b.- seen that t'tie potent-lal difj'erence across the diode is on the o.,der of 550 millivolts. This potential differelice is -faphical@iy rep.,-esented by operating poi:it 103 on tlac di,@de charac+erist-IC 45 curve sho,,vn in FIGUP,7H- 1. Clearly Nvlie-,i operati,@g thils, the diodo represents a v-,rj small f.'rward iii-ipedaiace (on the order of 30 ohms). With the a-oplicat;on of a set clock puls-. a@ time period t4 current is passed fro--n source 303 via diode 310 and diode 302 to the low level 5o source connected to the cathode of diode ""02. Thiis, it wiil be seen that the switching cirrent which in the previous case was passed through the ttinriel d-.ode is no-iv passed throu,ah the inplit diode and eff-ectii@-'-y bypasses the ttinnel diode vvhcreby the tlinnel diode operatin.@ sta"e 55 is not q@'tTected. T@'iough the@-e is aettial'Y a current sharing bctwpe@-1 diode 302 and tunnel dicde 100, the small currer,.t flow throtigh ti@e ti.,n-Aiel diode is ilisufF@cieDt to switch the ttinnel diode to the hi,-h level@ operatir@g co-nd;@tion. Conseqtieiitiy, the anode of the tunnel diode 300 60 and the otitput diodes connected thereto remain at the low lev--l poten,ial of approxiriiately +50 millivolts. Wh.-n the reset sig-@ial is apiolied to stage Pl at tirf,,e period t6, there is no actual rese'@ting of the tlinnel d@ode 300 inasmuch as the diode was not previolisly set to the 65 high voltage condition. As showil in F'LGURE 4, the arbitrary i-lput signal supplied to input PI chan@es from thp- low level si,@nal -500 millivolts to the higla level si,-ial of -50 mi'llivo@lts a@'ter tii-ne period t7. The input si.@iial ther. c,,n,,iniies at the 70 bigh level. At time period t3, the set clock si.-nal is applied to the circuit via clock source 308. As deser@.bed supral the positive going signal siipp'@ied by source 30-via diode 310 raises the potential at the anode of tunnel diode 300 inasmuch as the input diodes are baclr-biased 75 and cannot provide a current path. The tunnel diode 300
[4]7 is switched from the low voltage state to the high voltage state and a high level output si.-nal is provided at the anode th-.reof and at the anodes o.'L the R output diodes 312. Clearly, output Pi (the output signal from stage PI) may be considered as the i-.iput si.- nal to stage Nl. Thus, at time period tO throu-,h time period I the si,-,Ial ar,plied to the anode of input diode 112 is a hi.-h level si-.nal of about +500 mil'ivolts. Morco@,,er, siice th-- tulinel diode 322 ;s init,' ally assumed to be reset to the low volta,-c condition, the cathode thereof as well as the cathode of input diode 311@ resides at approximately - 50 millivol'ts. Clearly, the poten'lial diffe.-ence across the input diode is cii ttie order of 550 millivolts which is r--prescnted by operating poirt 108 on the -%I-I characteristic show@i in -.1@IGURE 1. Clearly, in this op-.ratinlpoi-@it t'@ic forward impedanc-- of th,- input diode is relatively low. Tiiere@lore, witli the application of the set clock si.-nal (a ne-.ative-goiiig sigrial w-@'th respect to ground potential) at time period tl, cvrrent passes through diode 314 to source 31.6. Iriasmuch as diode 312 is a r--Iatively low impedance wh-@.i fory-iard biased, a curre-@it sliar-'noperation obtains and some of the current wbich prev;ously passed throu-,h and switched ttinnel diode 322 now r)asses through the diode 312. ConseWiently, the tunr.ei diode 322 is ro+l switchcd and the i)otential at the cathode thereof rempins at -50 miili,7olts. Tlus, it will be seen that the otitput si.-nal Ni (the output sign-RI suppl;ed by stage NI), rema;ns at the higl@i level or -50 millivolt stage. After tiine period t2, the output si,-nal PI ciianges from +500 to +50 millivolts inasmuch as the sta,-e PI reset signal has been applied by clock source 31- 5 to stage PI. Therefore, ti%e potential value existing across input diode 312 drops to approxiriately 100 millivolts whereupoii t,@e diode is biased at about the operating point represented by 106 i@i FIGURE 1. At this operatin,- po-int the diode is a hi,-h impedanc-,. With the ai)plica'L-lop. of the stage NI reset signal at time peiiod t3, there is no change in the oul,put of the circuit (stage NI) i-@iasmuch as the t-Linnel diode 322 @.vas not switched prior to 'che applicatio-@i of the reset signal and will not be reswitch.-d thereby. As previously roted, the iiput signal to sla.-e NI was sNv.;tch-,d to a low lev--l signal at time period t2. Thus, d-Lirin- time poriod tS tl,,e application o't the stage NI set clock signal (a ne.-ativ.- going si-,nal with respect to ground) draws ctirrent through diode 314. With the precedin.- clock puls.-, current was dranvn through diode 312 from source 306. However, at the application of a clock sianal at time neriod tS the diode 312 is an extrem,-Iy liigh impedance and cannot pass ctirrent therethrou.-Ii. Therefore, current must pass through the tunn-,l diode 322. This currerit passage is effective to switch the ttinn--l diode 322 from the low voltage op.-ratin-, condition to the hi.-h volta.-c o@)erati@,-g condition. With "he switchin- of tlae tunnel di@de, the potential drop thereacross s,,vitches from 50 to approxitnately 500 millivolts. Inasmuch as the cnode of the diode is grounded, the calhode exhibits a potential of approximately -500 millivolts. Thiis, at time period t5 the output si.-nal provided by s,ale NI switcbes from the high level -50 milli"i volts signa to the low level --500 millivolt signal. This low le-v-.1 output si.-nal exists at the cathode of tlinvel diode 322 (as well as the cathodes of output diodes 324) throu,@h to time period t7. The r-.s-.t clock si---nal is a-oplied to the tunnel diode 3-i@2 at time p.riod t7 ' This reset si-nal, as stated supra, switches the tunnel diode 322 fro--i the hi,-h level ot).-ratin.- condition to the low volta,-c operating conditio.-i. When the tunnel diode switches back to the low voltage operatin- condition, the potential at the calho(le thereof s,,i,itches from -500 to -50 millivolts. At time period t3, it is seen that the oi.itput s:gnal froiii sta.-e PI (the inpiit to sta-,e NI) 'tcL swi ,-s from the low level to the high level signal. It is also observ-,d that at t;.ne pe.-iod tiO the input signal 3,198,959 applied to sla,-e Ni switelies from the hi.-h lcve'i to the low level signal beca-dse of the reset si.-nal supplied to sfa-,e Pi. Inasmucii as stag-- 1.11 Ni,as not sampled by a s@-t cloc'@@ si,-nal duri.,l,- this tinic theze was r,.o change in the outrut supplied by sta,-e NI. The output signal supplied by stage NI via the R output diodes 324 may be considered to b@- the input signal to stage P' via Q input diodes 324, 324a. Stage P' is somewhat different from the other standard stages in the 10 system. This sta@.e (P') is a type of hybrid NOR circuit in that an inversion of the input signal is provided. Moreover, the tunnel diode is connected at each of its electrodes to a different substantiauy constant current source. The anode of the tunnel diode 330 is connected to the poj5 tential source 332 via the resistor 356 while the cathode of the tunnel diode is connected to potertial source 328 via resistor 326,. Inasmuch as potential sources 332 and 328 are of the same magnitude (though of opposite polarities) the tunnel diode is eff-ectively :floating about 20 -round potential. Consequently, the potential drop across the tunnel diode is exhibited such that approximately one-half the potential drop is exhibited as a positive potential with respect to ground at the anode thereof and the cathode thereof exhibits al)proximately one-half 25 the potential difference across the tunnel diode as a negative potential with respect to ground. For example, with a typical gallium arsenide tunnel diode the low voltage biased potential would produce a drop of approximatelyy 100 to 150 millivolts across the tunnel diode. 30 In this condition, the anode of the tu-.inel diode 330 would exhibit a potential of beliveen +50 and +75 millivolts whereas the cathode of the tunnel diode ,viDuld exhibit a potential of approximately -50 to-75 millivolts. Moreover, the functional application of the P' stage is some@'5 what different than the standard AND-OR stage operation in that the tunnel diode is sw@'@tched from the low to the high voltage operating conditio.,l when clrrent passes through the tunnel diode via the input diode. The operation of the circuit is more clearly understood 40 in terms of the waveforms shown in FIGURE 4. Thus, it is assumed that the tuinel diode 330 is initially reset to the low voltage operating condition. Even if this assumption ,iere not made the initial signal applied at the tiine period tO is a reset si.-na which would drive the 45 tunnel diode to the low level operating condition an@way. It is seen that the input signal supplied to the Q input diodes 324, 324a by sta.-e NI, is a W-,h level or -50 nillivolt signal between time period 10 and time period t5. -Tnasmi,-ch as the tunnel diode exhibits a po50 tential at the cathode thereof on the order of -50 to -75 millivolts, the input diode 324 is effectively back-biased and presents a large irnpedance in that branch of the circuit. Consequently, when the sta.-e P' set clock signal is applied by source 334 via diode 336 at time period t2, 55 the tunnel diode 339 is not s-,vitched. The tunnel diode 330 is not switched because sources 328 and 332 are relatively high potentials (a ma.-nitude on the order of 10 volts) and the resistors 326 and 356 are large impedances (on the order of 3000 ohms) whereby substantial60 ly constant current sources are provided at the anode and cathode of the turnel diode. These constant current sources supply currents on the order of 3 to 4 milliimperes through the circuit (the precis.- current supplied is dependent upon the requirements of the tunnel 65 diode utilized). The clock source 334 supplies an input signal of about 0.5 volt via diode 336 which has a forward impedance of about 30 ohms. When the potential is considered between source 334 and source 323 via diode 336, resistor 326, and tunnel diode 330, it will be seen 70 that the small voltage change of 334 via the large impedance in the network will produce a substantially insignificant increase in current flow through the circuit Nvhich will be substantially immaterial in the operation of the tunnel diode. That is, for sake of example, consider 75 a tunnel diode 330 biased about 0.7 of lp where Ip is 5
[5]mifliamperes. Thus, the turnel diode would exhibit a current on the order of 3 to 4 inilliamperes. The currenl supplied via source 334 and diode 336 would be on the order of .15 mi!Hampere. Clearly, .15 milliampere signal is insufficient to drive the tunnel diode from the 4 milliampere operatin.- stage beyond the 5 milliampere (peak current) operating stage as required in order to switch the tunnel diode to the high voltage operating condition. Thus, so lon.- as the input diodes are reverse-biased the tunnel diode will not be switched to the high voltage operatin.- coridition by the apolication of the set clock pulse. As shown in FIGURE 4, the input signal supplied to stage P' chana.es from the high level to the low level s;gnal at time period t5. Thus, the potential at the cathode of input d@'ode 324 changes from -50 to -500 millivolts thereby creating a potential difference across the diode of approximately 450 millivolts such that the diode is operating in a region represented by point 108 in FIGURE 1. Therefore, the input diode is now forward-biased and presents a relatively low forward impedance (on the order of 30 ohms) in the input circuit. Consequently, -,vith the application of a stage P' set clock signal at time period t6 curre-,lt will fiow from source 334, through diode 336, tunnel diode 330, and input diode 324 to source 318. Now it wiil be seen that the impedance in the current path comprises only diode 336 (forward impedance on the order of 30 ohms), input diode 324 (which has a forward impedance of approximately 30 ohms) and the forward impedance of tunnel diode 330. Thus, tne current now supplied to the tunnel diode 330 by the potential increase of source 334 is in tho range of 5 to 10 milliamperes. Clearly, in the illustration previously noted, the tunnel diode 330 may b-- swilehed to the high voltage operatin.- condition by this current. With the switchin-. of the tunnel diode to the h@'@gh operatina condition, the potential at the anode and cathode thereof switch to approximately 450-500 millivolts. It may be seen that this switching of the tunel diode vviu now back bias the input diode 324. However, this change in the imp@-dance of the input diode 324 is immaterial at this time. Considering this operation in terms of pc@'Lential, it may be seen that similar results are obtained. The tunnel diode is initiaey biased such that the anod@- resides at about +50 milevolts and the cathode resides at about -50 millivolts. When the input si.-nal applied to diodes 324, 3'@4a ;@s a hi.-h level signal (-50 millivolts) the diod-,s 324, 324a are effectively cutoff. Thus, when the potent-ial of the anode of tunnel diode 330 is raised toward +500 millivolts by the application of a set clock signal by source 334, the maximum potential drop across the tunnel diode is on fac order to the peak potential (or less) in millivolts. That is, the clock signal is about +500 n-lillivolts and diode 336 drops about 300 millivolts thereacross vvhereby the anode of tunnel diode 330 resides at a maximum of about @+200 millivolts. The potential at the cathode of tunnel diode 330 tends to rise to aboilt +100 milli@,,olts. Since the potential drop across the tunnel diode remains below the peak potential, the tunnel diode will not switch to the high voltaae operating state. Vihen the input si.-nal is a low level si,-nal (-500 millivalts) the cathode of tunnel diode 330 initial'iy resides ,at about - 150 millivolts and the anode thereof resides at about -50 millivolts. With the application of a clock sianal (+500 millivolts) the anode of tunnel diode 330 rises to about +200 millivolts. These potential values produc-. a 350 millivolt potent@al difference across the tunnel diode vihereby the tunnel diode switches to the hi.-h volta.-c operating state. It is to be understood ' of course, that the description of the operation in ter@;s of the potentials or the currents are mutually compatible and interdependent. In particular, the operating characteristies of each component must be investigated. The potential at the anode of tunnel diode 330 is sup3,198,959 plied to the anodes of the R output diodes 338 until the reset clock signal is supplied to tunnel diode 330 by soil-ree 341. With the apl)lication of the negative going reset signal the magnitude of -kvhich is approximately -500 millivolts, the potential at the anode of tunnel diode 330 is switched toward about - 1"@O millivolts. Inasmuch as t@he pat-,ntial applied to both th@- anode and the cathode @of the tunnel diode is of the same order of magnitude, the potential difference across the tunnel diode is approxilo irately zero volts. Clearly, the tunnel diode will Switch to the low voltage joperating condition when the potential difference thereacross is below the peak voltage for the tunnel diode. Thus, with the application of the stage PI reset signal at time period tS, the tunnel diode 330 is 15 switch@-d back to the low voltage operating condition and the volta,-e produced at the anode thereof as well as at the anodes of output diodes 338 is oia the - order of +50 mi-Ilivolts. Inasmuch as thp- input signal applied to input diodes 324 is a high level signal during the applioation of 20 further clock pulses, stage P' continues to produce a low level output si.-nal, As a preferred imptovement which is not absolutely necessary to the circuit operation, a clamping network @comprising source 342 and diode 340 is provided. 25 Source 342 may provide a pulsatin.@ potential (about 300 millivolt pulses) which is syncronous with the clock poential s@,ipplied by sotirce 346 in stage N2 or may supply a substantially constant potential of about +150- millivolts. TI-ds network serves to clamp the cathode (>f tun30 nel diode 330 to a predeterniined potential (O to -150 -rnillvotes) whereby -a larger fan-out :Is possible. That is, if not clamped, tunnel diode 330 would be fre6 to ff oat relative to grouiid potential and the anode potential would tend to drop when an output was produced. How35 ever, tl-ie clamping network limits the "free-swipg" or "floating" of the tunnel diode wh@-reby virtually the entire output poteiltial is utilizable. The output signal from stage P' is, Df course, the input si,-nal to stage N2. The operation of sta,@e N2 is 40 identical to the operation of previously described stage Ni. That is, when the input signal is a high level (-500 niillivolts) si,-nal a set clock sig-rial applied to s@tage N2 will have no effect on the tunnel diode therein and the output signal will rema;n as a hi.-h level (-50 millivolt) 45 si-nal. On the contrary, hovvever, when the output from the P or P' @stage is a low level (+50 millivoli) signal, the applicati<)n of a set clock sign-al to stage NZ wil.I cause the tunnel diode 352 to switch to the high volta,@e operating condition whereby the output signal becomes a low 50 level (-500 millovolt) si.-nal. Thus, for example, at time period tO the outpiit signal from sta.-e P' or the indut si,@nal to stage N2 is a low leiel signal of +50 milliv@lts. As in the case of diode 312 in sta,@e Ni, input diode 338 is -considered to be a high impedance inasmuch as tunnel 55 diode 352 is assurned to have been initially reset thereby exhi-b@iting a potential of -50 volts at the cathode thereof. Therefore, the @output signal supplied by t-he anode of tunnel diode 352 to the cathode of the R output diodes 354 is a hi.-h level tor -50 mil@livolt signal. The sta.-e N2 60 reset clock ;signal applied to tunnel diode 352 at time period tl is of course of no @signiiicance inasmuch as the tunnel diode is @already reset. Howev-@r, with the application of the set clock signal at time period 13, current is drawn through tunnel diode 65 352, diode 344 and clock source 346. Alternatively considered, the clock signal (- 500 mil-livolts) -at clock 346 switches the potential at the cathode of tunnel diode to about -150 millivolts. This provides a potential drop across the tunnel diode which is -reater than the peak po70 tential of the tunnel diode. This current is of sufficient magnitude as described supra to cause tunnel diode 352 to @witch from the low voltage operating condition t-o the high voltage oper-ating condition. When tunnel diode 352 is switched to the high voltage operating condition, 75 the pot@-ntial difference thereacross is on the order of 500
[6]millivolts. Inasmuch as the anod.- of the tunnel diode is -negativ-- vallie outputs whereas the P' stage utilizes ne@@agrounded, tie cathode thereof exhibits a potential of approximately -500 millivolts. This - 500 millivolt potential is of coarse applied to the anodes of the R outt),at diodes 354 thereby prov,.dir@ a low level output si,-iial. Inasmuch as the tunnel diode is a bistable device, the output si.anal remains at th.- same level u-@itil the appl;cation of the reset clock si,-nal at time period t5. As de,scribed supra, ths positive goiiig r.-set signal causes tunnel diode 352 io switc'h from the h,:gh voltage to the low volta.-c operatin.- condition - ,vhercupon the poteitial at the cathode thereof switches from -500 to ---@50 millivolts. The -50 millivolt potential is Lapplied to th@- cathodes of the R output diodes 354 thereby providing a high level output si-nal. ',Afith the application of the set clock sign,,il at time period t7, it is seen that the input di(>de 333 is a low fon-@ard impeda-@ice inasmuch as the output Si,'nal supplied by stage P' is a Iii@h level cr +500 millivolt si,-nal. Thus, with th-, applicat;oi-i of th.- ne.-ative going set clo@-k si-nal, current flows throu.-Ii t'iie input diode and diode 341A 'Lo the sourc-, ':1,46 and tur@ncl dio-ale 352 is not affected. Actually, a small cu.-rent iiiay be drawn through the tunnel diode but tMs current is insu.,Rcient to cause the tunnel d;ode tc) switch. Consequ.-ntly, the output potential at the cathode of tunnel diode 352 remains a'L -50 millivolts. The reset clock signal applied at tim,- period t9 of coiirse is not necessary inasmuch as the tunnel diode need not be switched back from the hi.-h voltaae to the low volta, operatng state Clearly, these component valties and parameters are illustrative only and modifications may be made in the circuit without materially alterin@ the inventive concepts descr'rbed. CerLain modifications are @- uggested in the circuit of FIGURE 5. Thus, it has been demonstrated that the typical P and N stages provid@- typical ANDOR complementary lo,-ic. In addition, a P' stage has been sho@vn to pro-,,ide a negation gate or an inversion function of the operation of the normal P sta,@e. As demonstrated above, this systeni is then :capable of providin.- AND-OR logic and a hybrid type of NO.R lo.-IC. Referrin@ now to FIGURE 5, there is s@'@own another embodiment of the lo.-ic system propos-.d. In this embodiment, components ",hich are similar to components shon@in in the embodiment shown in FIGURE 3 or setve !iimilar functions have the same last two di-its-only the first di.-it is chan.@ed f.,om a 3 to a 5. For example, the tunnel diode in sta,,e PI in FIGURE 3 is tunne! diode 300 whereas a siinilar diode in stage PI of FIGURE 5 is tunnel diod.- 500. A variation in the e-mbodiment shown in F--TGURE 5 substitutes a bipolar clock for the separat@- set and reset clo-,ks. This clock source is connected to the associated circuitry by a resistor. The r-ircuit operation is substantially id,-ntical iii principle with that of the eircuit shoi@in in FIGU-RE 3. Another distiction between the tv,,o embodirtients, is th-at tne embodim.-nt of FIGURE 3 -includes a Pe.@ation stage P' v,,hich inverts the s;.-nals of the P sfage @iii-creas F,-GURP 5 shows a negation sta.@e or inversio-.l sta,@e 'N' which inverts the op,-ration of an N sta.-C. For purpos--s of illustration, in FIGURE 5 th,-re is shown conn--cted in series ,sta,@e PI, sta,- e N', stage P2 ald sta-e N2. As noted supra, sta--. PI of FIGURE 5 is identical to sta,,,e, PI of FIGURE 3. Similat.1y, stage P2 of FIGTJPE 5 is identical to stage PI of eitlier 13g,-,re both in co,.iii,-uration and in operation. In order to differeTiHate between the cc)mp(>nents of sta,-e PI and sita,@e P2 the same r--fereTice nuni-.rals are utilized with the componeits of stage P2 bein- des;,-nated by a prime. Stage 1112 of FIGUR'@Q 5 .is identical to st-a-e N2 of FIGU-P,:E 3. Thus, F.TGURE 5 omits the utilization of a P' sta,-e but inserts sta,@e N' in place of - ,tage NI Gf FIGURE 3. In theary, sta,@e N' is similar in coti-figura@tion and op-- ratio.,i to sta,@e P' with the exception that ti@- outpuls thereof are inv-@rted. That is, sta- N' utilizes positivc value i@i ,e pulls and i)i7odLTces tive value inputs and produces positive value outputs. In pai-ticular, the .-allium arsenide tunnel diode 530 of sta.-a N' of FIGURE 5 has the anode ithereof connected via resistor 556 to a terminal of potential sourca 532 which is positive with respect to ground. Si:rnilarly, poteptia,@ source 523 has a n.-gative terminal thereof connected to the c@ithode of t'@c tu-rinel diode via re,@@stor 525. Mlith the application of a set clock signal which is negative-.-oin.- with respect to ground by source 534 via resistor 53.5 to the catho,'Le of tunnel diode 530, current is dravin throu@ga the tunnel diode. The magnitude of th-. current is d-@termined (similar to the P' sta@@e) by the forward impedance ol' input diode 512. Tlat is, if the 15 input diode 512 is a hi@-h impedanc-. t@lie current path betw,-en sotir.-e 53-) and source 534 is via resistor 556, tunnel diode 530, and resistor 536. As deserib-.d supra, the amou-it of current add@-d to the cur@rent flow normally passing throli,@h tunnal d;ode 530 via this path is a negli 20 -ible amount and is insLr'Rcient to switch the tunnel dicde. Or. the other hand, however, if diode 512 presents a low forward impedance, th-, current path for a set clock sianal s,@ipplie-d by source 534 is from source 506 to source 534 via resistor 504@, diode tunnel diode 530 and resistor 25 536. As described supra, this path Dermits the addition of a substantial a-mount of current to the current flow @h throu@ the tunnel diode 530 whereupon the tunnel diode is switch.-d from the low voltage operatiii@ condition to -the high volt-,tge operatin@ condition. Th switching of .-he tunnel diode chan,@es the potential value at the cathode thereof from approximately -50 millivolts to approlx ately -500 millivolts. Once again, the clamping Circuit comprising source 542 and diode 540 is uti]Led during -ti'le resettin@ of the tunnel diode as well as the 35 cic)Gking of tunnel diode 500'. The operation of the clanipi@i.- circiut shown in FIGURE 5 is similar to the OPe-ration of th-- circuit shoi@,n in FIGLTPE 3. Iii describing the operation of the system, FIGURE 6 'xvhich is a tinin,@ diagram for the syst@-m shown in FIG40 URE 5, may be compared to the timin,@ diagram shown in FIGURE 4. It will be seen that the timing relationships between clocks A, B, C and D (the clock signals applied to the various stiges in the system) are identical tc) those shown in FIGURE 4. Moreover, the arbitrary 45 indut signal supplied to sta@e PI is similar to the arbitrary input supplied to the syste@,'n sho@vn in FIGURE 3. That is ' the input PI signal is a high level kl-50 millivolt) si.,nal fron tinie period tO t,"@rough time period t2. At that time, input PI s,@@,itches to a low level (-500 milli50 vllt) signal and remains thereat Lintil time period t7 vlhe@n the input PI si 'nal switches back to t, e hi,@h level 50 millivolt) si@r,@al. Inasmuch as sta,,e PI of FIGURE 5 is identical to stage PI in FIGUr-,,E, 3, the output signals therefrom are also ideiitical, That is, the ou'put li 5 P.1 si,@nal is a hi,@ll level (+500 millivolt) signal from tir@ic p@-riod ti) throu.-h to time per;od t2. T-Ilis signal is a hi,@h i-,V-'l si-nal ;n response to the hi,@h level input si,@nal being appli'ed 'Lo the input diode 502 simultaneousIY with the positive going set clock A signal bein.- appl;cd 00 to stage PI at tinie period to. The output PI signal is switched. to the low level (+50 roillivolt) signvl with th-- application of the ne,.,ative @Oin, reset si@ nal to sta-e PI at tiine p.rio-I t2. Tii@- al@plication of a seit clock A sigiial at tinl-- period t-'l in coincidence VIith the low level C5 input sign@l applied to stage PI will -,iot cause the ttinnel diode SOO to switch whereby the outplit signal reiiiains at the low le-vel si-.nal. At tiin-- period t$, the set clc)ck A Eignal is a.@ain applild to sta.@e PI. This time the clock si,@nal is aPPlied simuitaneously ivith a hi,@h lev-,] input diode 502. Consequently, turi70 il'Put signal at the iiel diod-- 500 is sin,,itched from the low voltage to the hi,@h voltage operating conditio@i whereupon the outpul signal obtained from the anoee thereof switches from +50 to +500 millivolts. A,@ain, at time period flO the 75 res-,t c'ock A si-t-lal causes tunnel diode 500 to be
[7]switched from the hi.-h volta.-e to the low voltaae op@@ratin,@ condition whereupon the outplit si.-nal derived at the -anode of the tunnel diode rev,@rts to the low or +50 millivolt signal. The output PI signal is applied to the input of stage N'. As prevously described, the tumiel diode is assumed to be initially reset to the low voltage operating condition. Consequently, tunnel diode 530 exhibits a po',ential ofapproximately -50 rq;.Ilivolts at th-- cathode and approximately +50 millivolts at the anode thereof. At tii-ne period tl, however, the set clock B signal is applied to stage N'. This clock signal is applied coincidentally with a hi-,h level input signal applied by inout diodes 512. Consequently, current flow throu.-h tunnel diode 530 is defined and delimited by the path impedance of diode 512, tunnel diode 530 and resistor 536. In view of the small value of impedance in the circuit, the clirrent is sufficient to switch the tunnel diode from the low vc)ltage to the bigh voltage operating cond-ition. Thus, the potential at the calhode of tunnel diode 530 switches from -50 -Lo -500 irillivolts and the poter@tial at the anode switches from +50 to +500 m:@llivolts. The application of the reset clock B si.-nal at time p.-riod t3 res-.ts the tunne-'L diode 52-0 where-apon the output si.-@-ial or the potential at the cathode trer-.of is switched back to -50 millivolts. In addition, the potential at the anode thereol' sw'itches to +50 millivolts thereby to effectively ready d:.ode 512 for further input sional applications. The set clock B signal supplied to stage N' at time period t5 is in coincidence with a low level input signal at the input diodes. The inplit d-lodes exhibit a high inpedance whereupon the current ffow through tunnel diode 530 is limited by the impedance in the path from source 532 and includin.- resistors 536 and 556, and ti-innel diode 5'00. The large path impedances and the small clo-.k signal produce a small current which is not sufecient to switch the tunnel diode to the high voltage operating condition. Conseqtiently, the potential at the cathode of the tunnel diode remains at the - 50 millivolt level (and the anode remains at +50 millivolts). The set clock B signal at time period t9 is presciited in coincidence with a high level input signal to the N' stage. As before, the diode presents a low forward impedance and the curre-iit supplied to the tunnel diode is su--iqcient to switch the tunnel diode from the low voltage to the high voltage op--rat;nl- conditio-@i. Consequently, tne cathode thereof exhibits a potential of about -500 millivolts. A comparison of the waveforms shown in FIGURE 4 and FIGURE 6 will show that tlie operational waveform for stages NI and N' are inverted. That this is the correct situation is clear inasrruch as stage N' is defined as performiiig the ne.aation oi- irv.,rsion operation of an N stage. Referrin.- now to the stage P2, it is to be u-tiderstood that stage P2 operates identically to stage PI. Thus, the reset clock C signal at time period O assures that tinnel diode 500' is in the low volta,@e operating condition. Consequently, th-- outpat signal at t'@ie anod-, thereof is a low level (+50 millivolt) si-nal. The set clock C signal at tim,- period t2 is coincidental w-.th the application of a low level input si-nal (-500 millivolt) thereto ivhereby the tunnel diode is not switched to the high voltage operatin.- condition. Thus, the output si,@nal produced by sta.ae P2 remaiiis at the low level or +50 millivolt signal. The set clock C signal which is applied to sta.-e P2 at time period t6 is, bowever, applied in conj-anction with a hi.-h level (-50 millivolts) input signal which is ar,plied via input diode 524. These simiiltaneous si.-na'ls cause tunnel diod-. 500' to switch to the high voltage operatin- condition. That is, diode 524 presepts a high impedance and current produced by the clock signal passes through the tunnel diode. Thus, the output potential produced at the anode of the tunnel diode 500' switches from +50 to +500 millivolts. The potential 14 at the outpat of tunnel diode 500' remains at the high level si-nal until the application of reset clock C signal at tilue period tg, Nvhereupon the output of stage P2 switches to the low level or +50 millivolt signal. The applicat-on of the set clock C signal at time p--riod tIO is in co-'ncidence with a low level input signal whereupon tunnel diode 500' is iaot switched inasmuch as diode 524 presents a low impedance path to the current suppl@,@d by the clock source 503' and the output produced 10 by sta.e P2 remains at the low level signal. Th.- coml3arison of the waveform of the output signals produced by stage P2 with the outp@at waveform produced by stage P' shown in FIGURE 4 will show that these waveforms are ident-ical. That th@s is the case is coinci15 dental only -inasmuch as the irustrations presented produce such coincidence of signals. The illustrations shown are ilot meant to be limitative of the invention nor do they limit the operation of the invention nor is the operation ol. the invention Iiinited to the illustrations shown. 20 A review of the illustrations shown will make it c'@ear that tne system of FIGURE 3 uses a PNP'N co ation while the system of FIGURE 5 uses a PN'PN configuration. Thus, it will be seen that the middle two stages of both configurations are such that at least one 25 inversion staaa is included. Thus, in the particular illustrations presented, the otitput si-,nal produced by the middle two stages and supplied to the final stage should be idcntical. @.hat is, the signal produced by a combinatior. of NP' stages shodld be identical to the signal pro30 duced by a combinatio-q of P'N stages. It is to be understood that modifications in the operation may be developed whereby this particular condition is not true. Inasmuch as the input supplied to stage N2 in FIGURE 6 is identical to the input signal supplied to stage 35 N2 sho@vn in FIGURE 4, it is clear that the output signal supplied by sta.-e N2 will be ide-@itical in both cases. That is, at time period t3 a set clock D signal is supplied in conjunction with a low level input signal whereupon the tunnel diode 552 is switched to the high level volta.-e 40 operating condition because diode 512' is a high impedance and permits substantially no current flow therethroil-gh. The output t3otential at the cathode of the tunnel diode is, therefore, switched to approximately -500 millivolts. The tunnel diode is switched back 45 to the low voltage operating condition at ti-tne period t5 in response to th.- appecation of Teset clock D signal ivhich is i)ositive going with respect to ground. The set clock D si,-nal applied at time period t7 is incoincidence viith the application of a high level input signal to stage 50 N2. Clearly, this combination of signals will not prodlce a switching current through tunnel @ibde 552 since diode 512' is a low impedance and permits current flow therethrough. Thus, the cathode of tunnel diode will remain at the low level signal of about -50 millivolts. 55 It is to be understood, that this invention relates to a logic; system using complementary AND-OR logic as weR as inversion or hybrid-NOR logic circuits. Moreover, it is to be understood that each of the individual circuits, as well as the system embodiments, are to be 60 includedwit.@inthe-scopeoftheappendedclaims. Thatis, principles of operation as taught by the foregoing description as well as modifications thereto are to be the basis for the claims blit the claims are not to be limited in scope by the precise configurations of systems (>r cir65 cuits shown. Any modifications su,@gested to those skifled in the art wwch may be made to the circuit shown are raeant to b,- incl-aded within the teaching of this invention so long as the modifications made thereto do not alter the principle of operation of this circuit. 70 The embodiments of the invention in which an exclusive property or privilege is claimed are defined as follows. I
